Patents by Inventor Chia-Yu Hsu
Chia-Yu Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240182141Abstract: A multihull module is provided. The multihull module includes multiple power floats, an actuation interface controller, and a vehicle controller. The power floats are disposed on a vehicle. The actuation interface controller is coupled to the power floats, and is configured to control the power floats. The vehicle controller is coupled to the actuation interface controller, and is configured to provide a control signal to the actuation interface controller. The actuation interface controller controls the power floats according to the control signal.Type: ApplicationFiled: December 6, 2022Publication date: June 6, 2024Applicant: Metal Industries Research & Development CentreInventors: Kuang-Shine Yang, Chao Chieh Hsu, Ping-Hua Su, Tsung-Yi Lan, Chia-Yu Hung
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Publication number: 20240176093Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: ApplicationFiled: February 5, 2024Publication date: May 30, 2024Inventors: Chao-Chang HU, Chih-Wei WENG, Chia-Che WU, Chien-Yu KAO, Hsiao-Hsin HU, He-Ling CHANG, Chao-Hsi WANG, Chen-Hsien FAN, Che-Wei CHANG, Mao-Gen JIAN, Sung-Mao TSAI, Wei-Jhe SHEN, Yung-Ping YANG, Sin-Hong LIN, Tzu-Yu CHANG, Sin-Jhong SONG, Shang-Yu HSU, Meng-Ting LIN, Shih-Wei HUNG, Yu-Huai LIAO, Mao-Kuo HSU, Hsueh-Ju LU, Ching-Chieh HUANG, Chih-Wen CHIANG, Yu-Chiao LO, Ying-Jen WANG, Shu-Shan CHEN, Che-Hsiang CHIU
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Patent number: 11996484Abstract: A semiconductor device includes a substrate, two source/drain features over the substrate, channel layers connecting the two source/drain features, and a gate structure wrapping around each of the channel layers. Each of the two source/drain features include a first epitaxial layer, a second epitaxial layer over the first epitaxial layer, and a third epitaxial layer on inner surfaces of the second epitaxial layer. The channel layers directly interface with the second epitaxial layers and are separated from the third epitaxial layers by the second epitaxial layers. The first epitaxial layers include a first semiconductor material with a first dopant. The second epitaxial layers include the first semiconductor material with a second dopant. The second dopant has a higher mobility than the first dopant.Type: GrantFiled: May 13, 2021Date of Patent: May 28, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Hao Lin, Chih-Hsuan Chen, Chia-Hao Pao, Chih-Chuan Yang, Chih-Yu Hsu, Hsin-Wen Su, Chia-Wei Chen
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Publication number: 20240162833Abstract: A power supply unit supplies power to a load, and the power supply unit includes a power factor corrector, a DC conversion module, and an isolated conversion module. The power factor corrector is plugged into a first main circuit board and converts an AC power into a DC power. The DC conversion module is plugged into the first main circuit board and converts the DC power into a main power. The isolated conversion module includes a bus capacitor, the bus capacitor is coupled to the DC conversion module through a first power copper bar, and coupled to the power factor corrector through a second power copper bar. The first power copper bar and the second power copper bar are arranged on a side opposite to the first main circuit board, and are arranged in parallel with the first main circuit board.Type: ApplicationFiled: November 13, 2023Publication date: May 16, 2024Inventors: Yi-Sheng CHANG, Cheng-Chan HSU, Chia-Wei CHU, Chun-Yu YANG, Deng-Cyun HUANG, Yi-Hsun CHIU, Chien-An LAI, Yu-Tai WANG, Chi-Shou HO, Zhi-Yuan WU, Ko-Wen LU
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Patent number: 11967522Abstract: A method includes depositing an etch stop layer over a first conductive feature, performing a first treatment to amorphize the etch stop layer, depositing a dielectric layer over the etch stop layer, etching the dielectric layer to form an opening, etching-through the etch stop layer to extend the opening into the etch stop layer, and filling the opening with a conductive material to form a second conductive feature.Type: GrantFiled: April 25, 2022Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jyh-Nan Lin, Chia-Yu Wu, Kai-Shiung Hsu, Ding-I Liu
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Patent number: 11966241Abstract: A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.Type: GrantFiled: February 11, 2022Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Huan-Neng Chen, Yen-Lin Liu, Chia-Wei Hsu, Jo-Yu Wu, Chang-Fen Hu, Shao-Yu Li, Bo-Ting Chen
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Patent number: 11967570Abstract: A semiconductor package includes a base comprising a top surface and a bottom surface that is opposite to the top surface; a first semiconductor chip mounted on the top surface of the base in a flip-chip manner; a second semiconductor chip stacked on the first semiconductor chip and electrically coupled to the base by wire bonding; an in-package heat dissipating element comprising a dummy silicon die adhered onto the second semiconductor chip by using a high-thermal conductive die attach film; and a molding compound encapsulating the first semiconductor die, the second semiconductor die, and the in-package heat dissipating element.Type: GrantFiled: March 4, 2022Date of Patent: April 23, 2024Assignee: MediaTek Inc.Inventors: Chia-Hao Hsu, Tai-Yu Chen, Shiann-Tsong Tsai, Hsing-Chih Liu, Yao-Pang Hsu, Chi-Yuan Chen, Chung-Fa Lee
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Publication number: 20240120325Abstract: A stacked package structure and a manufacturing method thereof are provided. The stacked package structure includes an upper redistribution layer, a first chip, and an upper molding layer. The first chip is disposed on the upper redistribution layer and is electrically connected to the upper redistribution layer. The upper molding layer is disposed on the first chip and the upper redistribution layer, and is configured to package the first chip. The upper molding layer includes a recess, the recess is recessed relative to a surface of the upper molding layer away from the upper redistribution layer, and the recess is circumferentially formed around a periphery of the upper molding layer.Type: ApplicationFiled: May 31, 2023Publication date: April 11, 2024Applicant: POWERTECH TECHNOLOGY INC.Inventors: Pei-chun TSAI, Hung-hsin HSU, Shang-yu CHANG CHIEN, Chia-ling LEE
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Publication number: 20240099030Abstract: A bonded assembly includes an interposer; a semiconductor die that is attached to the interposer and including a planar horizontal bottom surface and a contoured sidewall; a high bandwidth memory (HBM) die that is attached to the interposer; and a dielectric material portion contacting the semiconductor die and the interposer. The contoured sidewall includes a vertical sidewall segment and a non-horizontal, non-vertical surface segment that is adjoined to a bottom edge of the vertical sidewall segment and is adjoined to an edge of the planar horizontal bottom surface of the semiconductor die. The vertical sidewall segment and the non-horizontal, non-vertical surface segment are in contact with the dielectric material portion. The contoured sidewall may provide a variable lateral spacing from the HBM die to reduce local stress in a portion of the HBM die that is proximal to the interposer.Type: ApplicationFiled: April 20, 2023Publication date: March 21, 2024Inventors: Kuan-Yu Huang, Sung-Hui Huang, Kuo-Chiang Ting, Chia-Hao Hsu, Hsien-Pin Hsu, Chih-Ta Shen, Shang-Yun Hou
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Patent number: 11934027Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: GrantFiled: June 21, 2022Date of Patent: March 19, 2024Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
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Patent number: 11927991Abstract: Embodiments of synchronized hinges for foldable displays are described. In some embodiments, a hinge may include: a first bracket coupled to a first shaft via a first arm, a second bracket coupled to a second shaft via a second arm, and a synchronization bracket coupled to the first and second shafts.Type: GrantFiled: May 12, 2021Date of Patent: March 12, 2024Assignee: Dell Products, L.P.Inventors: Christopher A. Torres, Enoch Chen, Anthony J. Sanchez, Chia-Hao Hsu, Hsu Hong Yao, Mo-Yu Zhang
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Publication number: 20240080505Abstract: A method, comprising: detecting an outage of at least one functionality in a live streaming; performing an first operation toward a second user terminal; storing data of the first operation in a database of the first user terminal; and displaying an effect corresponding to the first operation during the outage. The present disclosure may store the data of operation performed by the user terminal during outage and process the operation after the outage is recovered. Therefore, the streamers and viewers may feel interested and satisfied, instead of feeling anxious, and the user experience may be enhanced.Type: ApplicationFiled: June 23, 2023Publication date: March 7, 2024Inventors: Yung-Chi HSU, Hsing-Yu TSAI, Chia-Han CHANG, Yi-Jou LEE, Ming-Che CHENG
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Publication number: 20240065390Abstract: Bands for wearable devices include multiple band retainers used to maintain engagement between an assembly (e.g., a pair) of bands. Some band retainers may be permanently affixed with the band at a certain location of the band, while other band retainers can be removable. The removable band retainers can be moved to different locations of the band, thus allowing the band retainer to retain another band at different locations. As a result, the assembly of bands can be used with different users, and in particular, users with different wrist sizes. Moreover, using multiple band retainers can provide an engagement force between the bands to withstand higher-impact events, such as swimming and diving. Additionally, bands and band retainers may include one or more liquid-resistant and corrosion-resistant materials.Type: ApplicationFiled: August 18, 2023Publication date: February 29, 2024Inventors: Nicholas S. Brodine, Molly J. Anderson, Clement C. Tissandier, Osamu Yabe, Mengxi Zhao, Timothy S. Lui, Chia Tse Yeh, Kai-Yu Chung, Jen-Chun Hsu, Tatsuya Sano, Peng Li
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Patent number: 10351971Abstract: This application describes a method of preparation of a natural graphene cellulose blended fiber, which comprises using a graphite powder as a raw material for preparing a graphene solution, adding the graphene solution to a slurry formed by mixing and dissolving a wood pulp with N-methylmorpholine N-oxide (NMMO), removing the water content thereof to form a spinning dope, and then spinning the spinning dope by a Dry-Jet Wet method to manufacture a natural graphene cellulose blended fiber. The present method does not require a highly toxic hydrazine hydrate solution. Further, by increasing the adding ratio of the graphene solution in the manufacturing process, control of the antistatic properties and thermal transferring functions can be achieved, and thereby various requirements of different consumers can be satisfied. Besides, the fibers can decompose naturally after being used, and thus the product is harmless, natural, and environmentally friendly.Type: GrantFiled: September 29, 2016Date of Patent: July 16, 2019Assignee: ACELON CHEMICALS AND FIBER CORPORATIONInventors: Wen-Tung Chou, Ming-Yi Lai, Kun-Shan Huang, Shao-Hua Chou, Chia-Yu Hsu
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Publication number: 20190086912Abstract: A fault detection and classification method of multi-sensors is provided. The method includes the following steps: collecting the plurality of raw sensory data by the plurality of sensors, conducting the data normalization process and data augmentation process by the processor, conducting the feature extraction process by using the convolution neural network having the convolution layer, the activation layer, and the pooling layer, setting a diagnosis layer by connecting the plurality of feature maps to the single neuron, and obtaining the plurality of weight values of the plurality of sensors by using the activation function, and obtaining the abnormal probability by using the calculation of the multilayer perceptron neural network.Type: ApplicationFiled: December 18, 2017Publication date: March 21, 2019Inventors: Chia-Yu HSU, Wei-Chen LIU
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Patent number: 10190243Abstract: This application describes a method of preparation of a natural graphene cellulose blended meltblown nonwoven fabric, which comprises using a graphite powder as a raw material for preparing a graphene solution, adding the graphene solution to a slurry formed by mixing and dissolving a wood pulp with N-methylmorpholine N-oxide (NMMO), removing the water content thereof to form a spinning dope, and then directly preparing the natural graphene cellulose blended meltblown nonwoven fabric by a meltblown process. The present method does not require a highly toxic hydrazine hydrate solution. Further, by increasing the adding ratio of the graphene solution in the manufacturing process, control of the antistatic properties and thermal transferring function can be achieved, and thereby various requirements of different consumers can be satisfied. Besides, the fabric can decompose naturally after being used, and thus the product is harmless, natural, and environmentally friendly.Type: GrantFiled: October 3, 2016Date of Patent: January 29, 2019Assignee: ACELON CHEMICALS AND FIBER CORPORATIONInventors: Wen-Tung Chou, Ming-Yi Lai, Kun-Shan Huang, Shao-Hua Chou, Chia-Yu Hsu
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Patent number: 10190242Abstract: This application describes a method of preparation of a natural graphene cellulose blended spunbond nonwoven fabric, which comprises using a graphite powder as a raw material for preparing a graphene solution, adding the graphene solution to a slurry formed by mixing and dissolving a wood pulp with N-methylmorpholine N-oxide (NMMO), removing the water content thereof to form a spinning dope, and then directly preparing the natural graphene cellulose blended spunbond nonwoven fabric by a spunbond process. The present method does not require a highly toxic hydrazine hydrate solution. Further, by increasing the adding ratio of the graphene solution in the manufacturing process, control of the antistatic properties and thermal transferring function can be achieved, and thereby various requirements of different consumers can be satisfied. Besides, the fabric can decompose naturally after being used, and thus the product is harmless, natural, and environmentally friendly.Type: GrantFiled: October 5, 2016Date of Patent: January 29, 2019Assignee: ACELON CHEMICALS AND FIBER CORPORATIONInventors: Wen-Tung Chou, Ming-Yi Lai, Kun-Shan Huang, Shao-Hua Chou, Chia-Yu Hsu
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Publication number: 20170107650Abstract: This application describes a method of preparation of a natural graphene cellulose blended meltblown nonwoven fabric, which comprises using a graphite powder as a raw material for preparing a graphene solution, adding the graphene solution to a slurry formed by mixing and dissolving a wood pulp with N-methylmorpholine N-oxide (NMMO), removing the water content thereof to form a spinning dope, and then directly preparing the natural graphene cellulose blended meltblown nonwoven fabric by a meltblown process. The present method does not require a highly toxic hydrazine hydrate solution. Further, by increasing the adding ratio of the graphene solution in the manufacturing process, control of the antistatic properties and thermal transferring function can be achieved, and thereby various requirements of different consumers can be satisfied. Besides, the fabric can decompose naturally after being used, and thus the product is harmless, natural, and environmentally friendly.Type: ApplicationFiled: October 3, 2016Publication date: April 20, 2017Inventors: Wen-Tung CHOU, Ming-Yi LAI, Kun-Shan HUANG, Shao-Hua CHOU, Chia-Yu HSU
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Patent number: D1016283Type: GrantFiled: May 10, 2021Date of Patent: February 27, 2024Assignee: QUANTA COMPUTER INC.Inventors: Barry Lam, Chia-Yuan Chang, Jung-Wen Chang, Kao-Yu Hsu
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Patent number: D1022213Type: GrantFiled: December 27, 2022Date of Patent: April 9, 2024Assignee: QUANTA COMPUTER INC.Inventors: Barry Lam, Chia-Yuan Chang, Jung-Wen Chang, Kao-Yu Hsu