Patents by Inventor Chia-Yu Lu
Chia-Yu Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240144098Abstract: Aspects of the present disclosure provide an automated labeling system. For example, the automated labeling system can include an automated labeling module (ALM) configured to receive wireless signals and ground truth of learning object and label the wireless signals with the ground truth when receiving the ground truth to generate labeled training data. The automated labeling system can also include a training database coupled to the ALM. The training database can be configured to store the labeled training data.Type: ApplicationFiled: October 16, 2023Publication date: May 2, 2024Applicant: MEDIATEK INC.Inventors: Chao Peng WANG, Chia-Da LEE, Po-Yu CHEN, Hsiao-Chien CHIU, Yi-Cheng LU
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Patent number: 11934027Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: GrantFiled: June 21, 2022Date of Patent: March 19, 2024Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
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Publication number: 20230133295Abstract: A system and a method to assess abnormality are disclosed. The system is connected to an image capturing device and has multiple classification models and a processing module. Each one of the classification models is alternately trained by supervised learning and unsupervised learning. Parameters of the classification models are not identical. The processing module is connected to the classification models. The processing module receives a test image and outputs the test image to the classification models to respectively obtain multiple feature vectors of test images and to generate an abnormality assessment information.Type: ApplicationFiled: November 23, 2021Publication date: May 4, 2023Inventors: Chia-Yu Lu, Shang-Ming Jen
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Patent number: 11547904Abstract: An exercise assisting device and exercise assisting method are provided. The device performs the following operations: transmitting a first control signal, the first control signal is related to a motion demonstration video corresponding to an exercise course data; receiving a video stream of a user; analyzing the video stream to generate a motion recognition result corresponding to the exercise course data of the user, and determining whether a motion target value is achieved according to the motion recognition result and the exercise course data; and when the motion target value is not achieved, the motion recognition result and the motion target value are input into an expert suggestion model to generate a follow-up motion suggestion and to determine a follow-up motion demonstration video corresponding to the follow-up motion suggestion.Type: GrantFiled: December 5, 2019Date of Patent: January 10, 2023Assignee: INSTITUTE FOR INFORMATION INDUSTRYInventors: Chia-Yu Lu, Shang-Ming Jen
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Publication number: 20210138301Abstract: An exercise assisting device and exercise assisting method are provided. The device performs the following operations: transmitting a first control signal, the first control signal is related to a motion demonstration video corresponding to an exercise course data; receiving a video stream of a user; analyzing the video stream to generate a motion recognition result corresponding to the exercise course data of the user, and determining whether a motion target value is achieved according to the motion recognition result and the exercise course data; and when the motion target value is not achieved, the motion recognition result and the motion target value are input into an expert suggestion model to generate a follow-up motion suggestion and to determine a follow-up motion demonstration video corresponding to the follow-up motion suggestion.Type: ApplicationFiled: December 5, 2019Publication date: May 13, 2021Inventors: Chia-Yu LU, Shang-Ming JEN
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Patent number: 10733385Abstract: A behavior inference model building apparatus and a behavior inference model building method thereof are provided. The behavior inference model building apparatus converts a plurality of program operation sequences of a plurality of program operation sequence data into a plurality of word vectors through a word embedding model, and inputs the first M word vectors of the word vectors, corresponding to each program operation sequence data, into a generative adversarial network (GAN) model to train and optimize the GAN model. The behavior inference model building apparatus integrates the word embedding model and the generator of the optimized GAN model to build a behavior inference model.Type: GrantFiled: December 12, 2017Date of Patent: August 4, 2020Assignee: Institute For Information IndustryInventors: Chia-Min Lai, Chia-Yu Lu
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Publication number: 20190179906Abstract: A behavior inference model building apparatus and a behavior inference model building method thereof are provided. The behavior inference model building apparatus converts a plurality of program operation sequences of a plurality of program operation sequence data into a plurality of word vectors through a word embedding model, and inputs the first M word vectors of the word vectors, corresponding to each program operation sequence data, into a generative adversarial network (GAN) model to train and optimize the GAN model. The behavior inference model building apparatus integrates the word embedding model and the generator of the optimized GAN model to build a behavior inference model.Type: ApplicationFiled: December 12, 2017Publication date: June 13, 2019Inventors: Chia-Min LAI, Chia-Yu LU
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Patent number: 9412870Abstract: A device includes a substrate and a recess in the substrate. The recess has a bottom and sidewalls. The device also includes a first epitaxial layer over the bottom of the recess, and a second epitaxial layer over the first epitaxial layer and over the sidewalls of the recess, the second epitaxial layer having a different lattice constant than the substrate. The device further includes a third epitaxial layer over the second epitaxial layer and filling the recess.Type: GrantFiled: August 24, 2015Date of Patent: August 9, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: King-Yuen Wong, Chia-Yu Lu, Chien-Chang Su, Yen-Chun Lin, Yi-Fang Pai, Da-Wen Lin
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Patent number: 9281356Abstract: A method of fabricating a semiconductor device is disclosed. The method includes providing a substrate including an isolation region, forming a resistor over the isolation region, and forming a contact over the resistor. The method also includes implanting with a dopant concentration that is step-increased at a depth of the resistor and that remains substantially constant as depth increases.Type: GrantFiled: December 30, 2014Date of Patent: March 8, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: King-Yuen Wong, Chia-Pin Lin, Chia-Yu Lu, Yi-Cheng Tsai, Da-Wen Lin, Kuo-Feng Yu
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Publication number: 20150364602Abstract: A device includes a substrate and a recess in the substrate. The recess has a bottom and sidewalls. The device also includes a first epitaxial layer over the bottom of the recess, and a second epitaxial layer over the first epitaxial layer and over the sidewalls of the recess, the second epitaxial layer having a different lattice constant than the substrate. The device further includes a third epitaxial layer over the second epitaxial layer and filling the recess.Type: ApplicationFiled: August 24, 2015Publication date: December 17, 2015Inventors: King-Yuen Wong, Chia-Yu Lu, Chien-Chang Su, Yen-Chun Lin, Yi-Fang Pai, Da-Wen Lin
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Patent number: 9117843Abstract: An engineered epitaxial region compensates for short channel effects of a MOS device by providing a blocking layer to reduce or prevent dopant diffusion while at the same time reducing or eliminating the side effects of the blocking layer such as increased leakage current of a BJT device and/or decreased breakdown voltage of a rectifier. These side effects are reduced or eliminated by a non-conformal dopant-rich layer between the blocking layer and the substrate, which lessens the abruptness of the junction, thus lower the electric field at the junction region. Such a scheme is particularly advantageous for system on chip applications where it is desirable to manufacture MOS, BJT, and rectifier devices simultaneously with common process steps.Type: GrantFiled: September 14, 2011Date of Patent: August 25, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: King-Yuen Wong, Chia-Yu Lu, Chien-Chang Su, Yen-Chun Lin, Yi-Fang Pai, Da-Wen Lin
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Patent number: 9111768Abstract: Semiconductor devices, methods of manufacture thereof, and methods of forming resistors are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a first insulating material over a workpiece, and forming a conductive chemical compound material over the first insulating material. The conductive chemical compound material is patterned to form a resistor. A second insulating material is formed over the resistor, and the second insulating material is patterned. The patterned second insulating material is filled with a conductive material to form a first contact coupled to a first end of the resistor and to form a second contact coupled to a second end of the resistor.Type: GrantFiled: September 15, 2014Date of Patent: August 18, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Yu Lu, Shyue-Shyh Lin, Chin-Shan Hou, Kuo-Feng Yu, Tung-Heng Hsieh, Chih-Hung Wang, Jian-Hao Chen
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Patent number: 9070624Abstract: A described method includes providing a semiconductor substrate. A first gate structure is formed on the semiconductor substrate and a sacrificial gate structure formed adjacent the first gate structure. The sacrificial gate structure may be used to form a metal gate structure using a replacement gate methodology. A dielectric layer is formed overlying the first gate structure and the sacrificial gate structure. The dielectric layer has a first thickness above a top surface of the first gate structure and a second thickness, less than the first thickness, above a top surface of the sacrificial gate structure. (See, e.g., FIGS. 5, 15, 26). Thus, a subsequent planarization process of the dielectric layer may not contact the first gate structure.Type: GrantFiled: December 16, 2011Date of Patent: June 30, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jian-Hao Chen, Chia-Yu Lu, Tung-Heng Hsieh, Kuo-Feng Yu, Chin-Shan Hou, Hsien-Chin Lin, Shyue-Shyh Lin
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Publication number: 20150111361Abstract: A method of fabricating a semiconductor device is disclosed. The method includes providing a substrate including an isolation region, forming a resistor over the isolation region, and forming a contact over the resistor. The method also includes implanting with a dopant concentration that is step-increased at a depth of the resistor and that remains substantially constant as depth increases.Type: ApplicationFiled: December 30, 2014Publication date: April 23, 2015Inventors: King-Yuen Wong, Chia-Pin Lin, Chia-Yu Lu, Yi-Cheng Tsai, Da-Wen Lin, Kuo-Feng Yu
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Publication number: 20150001678Abstract: Semiconductor devices, methods of manufacture thereof, and methods of forming resistors are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a first insulating material over a workpiece, and forming a conductive chemical compound material over the first insulating material. The conductive chemical compound material is patterned to form a resistor. A second insulating material is formed over the resistor, and the second insulating material is patterned. The patterned second insulating material is filled with a conductive material to form a first contact coupled to a first end of the resistor and to form a second contact coupled to a second end of the resistor.Type: ApplicationFiled: September 15, 2014Publication date: January 1, 2015Inventors: Chia-Yu Lu, Shyue-Shyh Lin, Chin-Shan Hou, Kuo-Feng Yu, Tung-Heng Hsieh, Chih-Hung Wang, Jian-Hao Chen
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Patent number: 8921946Abstract: A semiconductor device includes a substrate including an isolation region, and a resistor disposed over the isolation region, wherein the resistor includes an implant with an inverse box-like dopant profile that minimizes resistance variation from subsequent planarization variation. A contact is disposed over the resistor. A method of fabricating such a semiconductor device is also provided.Type: GrantFiled: November 11, 2011Date of Patent: December 30, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: King-Yuen Wong, Chia-Pin Lin, Chia-Yu Lu, Yi-Cheng Tsai, Da-Wen Lin, Kuo-Feng Yu
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Patent number: 8859386Abstract: Semiconductor devices, methods of manufacture thereof, and methods of forming resistors are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a first insulating material over a workpiece, and forming a conductive chemical compound material over the first insulating material. The conductive chemical compound material is patterned to form a resistor. A second insulating material is formed over the resistor, and the second insulating material is patterned. The patterned second insulating material is filled with a conductive material to form a first contact coupled to a first end of the resistor and to form a second contact coupled to a second end of the resistor.Type: GrantFiled: June 8, 2012Date of Patent: October 14, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Yu Lu, Jian-Hao Chen, Chih-Hung Wang, Tung-Heng Hsieh, Kuo-Feng Yu, Chin-Shan Hou, Shyue-Shyh Lin
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Publication number: 20130328131Abstract: Semiconductor devices, methods of manufacture thereof, and methods of forming resistors are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a first insulating material over a workpiece, and forming a conductive chemical compound material over the first insulating material. The conductive chemical compound material is patterned to form a resistor. A second insulating material is formed over the resistor, and the second insulating material is patterned. The patterned second insulating material is filled with a conductive material to form a first contact coupled to a first end of the resistor and to form a second contact coupled to a second end of the resistor.Type: ApplicationFiled: June 8, 2012Publication date: December 12, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Yu Lu, Jian-Hao Chen, Chih-Hung Wang, Tung-Heng Hsieh, Kuo-Feng Yu, Chin-Shan Hou, Shyue-Shyh Lin
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Publication number: 20130157452Abstract: A described method includes providing a semiconductor substrate. A first gate structure is formed on the semiconductor substrate and a sacrificial gate structure formed adjacent the first gate structure. The sacrificial gate structure may be used to form a metal gate structure using a replacement gate methodology. A dielectric layer is formed overlying the first gate structure and the sacrificial gate structure. The dielectric layer has a first thickness above a top surface of the first gate structure and a second thickness, less than the first thickness, above a top surface of the sacrificial gate structure. (See, e.g., FIGS. 5, 15, 26). Thus, a subsequent planarization process of the dielectric layer may not contact the first gate structure.Type: ApplicationFiled: December 16, 2011Publication date: June 20, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd. ("TSMC")Inventors: Jian-Hao Chen, Chia-Yu Lu, Tung-Heng Hsieh, Kuo-Feng Yu, Chin-Shan Hou, Hsien-Chin Lin, Shyue-Shyh Lin
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Publication number: 20130119480Abstract: A semiconductor device includes a substrate including an isolation region, and a resistor disposed over the isolation region, wherein the resistor includes an implant with an inverse box-like dopant profile that minimizes resistance variation from subsequent planarization variation. A contact is disposed over the resistor. A method of fabricating such a semiconductor device is also provided.Type: ApplicationFiled: November 11, 2011Publication date: May 16, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: King-Yuen Wong, Chia-Pin Lin, Chia-Yu Lu, Yi-Cheng Tsai, Da-Wen Lin, Kuo-Feng Yu