Patents by Inventor Chia-Chun Chen
Chia-Chun Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12002768Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a molded semiconductor device, a first redistribution structure, and conductive vias. The molded semiconductor device comprises a sensor die with a first surface and a second surface opposite the first surface, wherein the sensor die has an input/output region and a sensing region at the first surface. The first redistribution structure is disposed on the first surface of the sensor die, wherein the first redistribution structure covers the input/output region and exposes the sensing region, and the first redistribution structure comprises a conductive layer having a redistribution pattern and a ring structure. The redistribution pattern is electrically connected with the sensor die. The ring structure surrounds the sensing region and is separated from the redistribution pattern, wherein the ring structure is closer to the sensing region than the redistribution pattern.Type: GrantFiled: August 27, 2021Date of Patent: June 4, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chih Huang, Chih-Hao Chang, Po-Chun Lin, Chun-Ti Lu, Zheng-Gang Tsai, Shih-Wei Chen, Chia-Hung Liu, Hao-Yi Tsai, Chung-Shi Liu
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Publication number: 20240176584Abstract: An apparatus comprising: a first plurality of inputs representing an activation input vector; a second plurality of inputs representing a weight input vector; an analog multiplier-and-accumulator to generate a first analog voltage representing a first multiply-and-accumulate result for the said first inputs and the second inputs; a voltage multiplier that takes the said first analog voltage and produces a second analog voltage representing, a second multiply-and-accumulate result by multiplying at least one scaling factor to the first analog voltage; an analog to digital converter configured to convert the said second analog voltage multiply-and-accumulate result into a digital signal using a limited-precision operation during a neural network inference operation; and a hardware controller configured to determine the at least one scaling factor based on the first multiply-and-accumulate result, or a software controller configured to determine the at least one scaling factor based on the first multiply-and-accType: ApplicationFiled: November 29, 2022Publication date: May 30, 2024Inventors: Chia-Yu Chen, Andrea Fasoli, Ankur Agrawal, Kyu-hyoun Kim, Chi-Chun LIU, Mauricio J. Serrano, Monodeep Kar, Naigang Wang, Leland Chang
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Publication number: 20240170326Abstract: A manufacturing method of a semiconductor device includes at least the following steps. A sacrificial substrate is provided. An etch stop layer is formed on the sacrificial substrate. A portion of the etch stop layer is oxidized to form an oxide layer between the sacrificial substrate and the remaining etch stop layer. A capping layer is formed on the remaining etch stop layer. A device layer is formed on the capping layer. A first etching process is performed to remove the sacrificial substrate. A second etching process is performed to remove the oxide layer. A third etching process is performed to remove the remaining etch stop layer. A power rail is formed on the capping layer opposite to the device layer.Type: ApplicationFiled: January 25, 2024Publication date: May 23, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Ming Chen, Kuei-Ming Chen, Po-Chun Liu, Chung-Yi Yu, Chia-Shiung Tsai
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Patent number: 11985508Abstract: An RF fingerprint signal processing device configured for executing a machine learning algorithm on a plurality of input signals. The RF fingerprint signal processing device includes a receiver-feature determination circuit and a classifying determination circuit. The receiver-feature determination circuit is configured to compute on the plurality of input signals in a neural network. The classifying determination circuit is coupled with the receiver-feature determination circuit, and the classifying determination circuit is configured to send feedback information of a receiver-feature component to the receiver-feature determination circuit. The receiver-feature determination circuit decreases the receiver-feature weight of the neural network. The receiver-feature weight is associated with the receiver-feature component, and the receiver-feature weight which is decreased is applied for computing an output value of the neural network.Type: GrantFiled: November 17, 2020Date of Patent: May 14, 2024Assignee: INSTITUTE FOR INFORMATION INDUSTRYInventors: Ting-Yu Lin, Ping-Chun Chen, Chia-Min Lai
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Patent number: 11985662Abstract: A user equipment (UE) includes one or more non-transitory computer-readable media containing computer-executable instructions embodied therein, and at least one processor coupled to the one or more non-transitory computer-readable media. The at least one processor configured to execute the computer-executable instructions to receive downlink control information (DCI) on a downlink (DL) channel of a non-terrestrial network (NTN), the DL channel reception ending in a first slot, and transmit an uplink (UL) transmission on a UL channel of the NTN in a second slot. The second slot is separate from the first slot by a timing offset, where a duration of the timing offset is dependent on a type of the UL transmission and a numerology of the UL transmission.Type: GrantFiled: September 30, 2020Date of Patent: May 14, 2024Assignee: FG Innovation Company LimitedInventors: Chien-Chun Cheng, Chia-Hao Yu, Hung-Chen Chen, Chie-Ming Chou
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Publication number: 20240128420Abstract: A display panel including a circuit board, a plurality of bonding pads, a plurality of light emitting devices, and a plurality of solder patterns is provided. The bonding pads are disposed on the circuit board, and each includes a first metal layer and a second metal layer. The second metal layer is located between the first metal layer and the circuit board. The first metal layer includes an opening overlapping the second metal layer. A material of the first metal layer is different from a material of the second metal layer. The light emitting devices are electrically bonded to the bonding pads. Each of the solder patterns electrically connects one of the light emitting devices and one of the bonding pads. The solder patterns each contact the second metal layer through the opening of the first metal layer of one of the bonding pads to form a eutectic bonding.Type: ApplicationFiled: December 6, 2022Publication date: April 18, 2024Applicant: AUO CorporationInventors: Chia-Hui Pai, Tai-Tso Lin, Wen-Hsien Tseng, Wei-Chieh Chen, Kuan-Yi Lee, Chih-Chun Yang
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Publication number: 20240115616Abstract: The present disclosure provides a method for treating liver cirrhosis by using a composition including mesenchymal stem cells, extracellular vesicles produced by the mesenchymal stem cells, and growth factors. The composition of the present disclosure achieves the effect of treating liver cirrhosis through various efficacy experiments.Type: ApplicationFiled: October 4, 2023Publication date: April 11, 2024Inventors: Po-Cheng Lin, Pi-Chun Huang, Zih-Han Hong, Ming-Hsi Chuang, Yi-Chun Lin, Chia-Hsin Lee, Chun-Hung Chen, Chao-Liang Chang, Kai-Ling Zhang
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Publication number: 20240122078Abstract: A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.Type: ApplicationFiled: December 18, 2023Publication date: April 11, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chia-Chang Hsu, Tang-Chun Weng, Cheng-Yi Lin, Yung-Shen Chen, Chia-Hung Lin
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Patent number: 11955154Abstract: A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.Type: GrantFiled: May 16, 2022Date of Patent: April 9, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Cheng-Tung Huang, Jen-Yu Wang, Po-Chun Yang, Yi-Ting Wu, Yung-Ching Hsieh, Jian-Jhong Chen, Chia-Wei Lee
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Patent number: 11945907Abstract: Provided are an LCP film and a laminate comprising the same. The LCP film is made of an LCP resin comprising a structural unit represented by Formula (1): -L1-Ar-L2- (1), wherein -L1- and -L2- are respectively —O— or —CO—; —Ar— is an arylene group. Formula (1) comprises structural units Based on a total molar number of the structural unit represented by Formula (1), a molar number of the structural unit represented by Formula (I) is in the range from 15 mole % to mole %, and a sum of molar numbers of the structural units represented by Formulae (I) and (II) is in the range from 80 mole % to 100 mole %. The LCP film has a thickness and a transmittance, wherein when values of the thickness (in ?m) and the transmittance are put into Formula (III), the obtained value is from 0.055 to 0.090. Formula (III): Log(1/TT %)/(Thickness)0.5.Type: GrantFiled: December 18, 2020Date of Patent: April 2, 2024Assignee: CHANG CHUN PLASTICS CO., LTD.Inventors: An-Pang Tu, Chia-Hung Wu, Chien-Chun Chen
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Patent number: 11948920Abstract: Provided are a semiconductor device and a method for manufacturing the same, and a semiconductor package. The semiconductor device includes a die stack and a cap substrate. The die stack includes a first die, second dies stacked on the first die, and a third die stacked on the second dies. The first die includes first through semiconductor vias. Each of the second dies include second through semiconductor vias. The third die includes third through semiconductor vias. The cap substrate is disposed on the third die of the die stack. A sum of a thickness of the third die and a thickness of the cap substrate ranges from about 50 ?m to about 80 ?m.Type: GrantFiled: August 30, 2021Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: I-Chun Hsu, Yan-Zuo Tsai, Chia-Yin Chen, Yang-Chih Hsueh, Yung-Chi Lin, Tsang-Jiuh Wu, Wen-Chih Chiou
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Patent number: 11931187Abstract: A method for predicting clinical severity of a neurological disorder includes steps of: a) identifying, according to a magnetic resonance imaging (MRI) image of a brain, brain image regions each of which contains a respective portion of diffusion index values of a diffusion index, which results from image processing performed on the MRI image; b) for one of the brain image regions, calculating a characteristic parameter based on the respective portion of the diffusion index values; and c) calculating a severity score that represents the clinical severity of the neurological disorder of the brain based on the characteristic parameter of the one of the brain image regions via a prediction model associated with the neurological disorder.Type: GrantFiled: March 16, 2018Date of Patent: March 19, 2024Assignees: Chang Gung Medical Foundation Chang Gung Memorial Hospital at Keelung, Chang Gung Memorial Hospital, Linkou, Chang Gung UniversityInventors: Jiun-Jie Wang, Yi-Hsin Weng, Shu-Hang Ng, Jur-Shan Cheng, Yi-Ming Wu, Yao-Liang Chen, Wey-Yil Lin, Chin-Song Lu, Wen-Chuin Hsu, Chia-Ling Chen, Yi-Chun Chen, Sung-Han Lin, Chih-Chien Tsai
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Publication number: 20240088224Abstract: A semiconductor structure includes a first gate structure, a second gate structure coupled to the first gate structure, a source region, a first drain region, and a second drain region. The source region is surrounded by the first gate structure and the second gate structure. The first drain region is separated from the source region by the first gate structure. The second drain region is separated from the source region by the second gat structure. A shape of the first drain region and a shape of the second drain region are different from each other from a plan view.Type: ApplicationFiled: November 14, 2023Publication date: March 14, 2024Inventors: HSING-I TSAI, FU-HUAN TSAI, CHIA-CHUNG CHEN, HSIAO-CHUN LEE, CHI-FENG HUANG, CHO-YING LU, VICTOR CHIANG LIANG
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Publication number: 20240086609Abstract: A system including a processor configured to perform generating a plurality of different layout blocks; selecting, among the plurality of layout blocks, layout blocks corresponding to a plurality of blocks in a floorplan of a circuit; combining the selected layout blocks in accordance with the floorplan into a layout of the circuit; and storing the layout of the circuit in a cell library or using the layout of the circuit to generate a layout for an integrated circuit (IC) containing the circuit. Each of the plurality of layout blocks satisfies predetermined design rules and includes at least one of a plurality of different first block options associated with a first layout feature, and at least one of a plurality of different second block options associated with a second layout feature different from the first layout feature.Type: ApplicationFiled: February 16, 2023Publication date: March 14, 2024Inventors: Cheng-YU LIN, Chia Chun WU, Han-Chung CHANG, Chih-Liang CHEN
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Publication number: 20240086612Abstract: An IC device includes first through third rows of fin field-effect transistors (FinFETs), wherein the second row is between and adjacent to each of the first and third rows, the FinFETs of the first row are one of an n-type or p-type, the FinFETs of the second and third rows are the other of the n-type or p-type, the FinFETs of the first and third rows include a first total number of fins, and the FinFETs of the second row include a second total number of fins one greater or fewer than the first total number of fins.Type: ApplicationFiled: November 22, 2023Publication date: March 14, 2024Inventors: Po-Hsiang HUANG, Fong-Yuan CHANG, Clement Hsingjen WANN, Chih-Hsin KO, Sheng-Hsiung CHEN, Li-Chun TIEN, Chia-Ming HSU
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Patent number: 11926698Abstract: Provided are a liquid crystal polymer film (LCP film) and a laminate comprising the same. The LCP film has a first surface and a second surface opposite each other, and the first surface has an arithmetical mean height of a surface (Sa) less than 0.32 ?m. The LCP film with proper Sa is suitable to be stacked with a metal foil, such that a laminate comprising the LCP film can have an advantage of low insertion loss.Type: GrantFiled: December 18, 2020Date of Patent: March 12, 2024Assignee: CHANG CHUN PLASTICS CO., LTD.Inventors: An-Pang Tu, Chia-Hung Wu, Chien-Chun Chen
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Publication number: 20240077479Abstract: A detection system and method for the migrating cell is provided. The system is configured to detect a migrating cell combined with an immunomagnetic bead. The system includes a platform, a microchannel, a magnetic field source, a coherent light source and an optical sensing module. The microchannel is configured to allow the migrating cell to flow in it along a flow direction. The magnetic field source is configured to provide magnetic force to the migrating cell combined with the immunomagnetic bead. The magnetic force includes at least one magnetic force component and the magnetic force component is opposite to the flow direction of the microchannel. The coherent light source is configured to provide the microchannel with the coherent light. The optical sensing module is configured to receive the interference light caused by the coherent light being reflected by the sample inside the microchannel.Type: ApplicationFiled: August 10, 2023Publication date: March 7, 2024Applicant: DeepBrain Tech. IncInventors: Han-Lin Wang, Chia-Wei Chen, Yao-Wen Liang, Ting-Chun Lin, Yun-Ting Kuo, You-Yin Chen, Yu-Chun Lo, Ssu-Ju Li, Ching-Wen Chang, Yi-Chen Lin
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Publication number: 20240077593Abstract: An optical radar includes an optical-signal receiving unit and an optical-signal pickup unit. The optical-signal receiving unit is configured to receive a reflected light. The optical-signal pickup unit is coupled to the optical-signal receiving unit and includes a first optical-signal filtering circuit and a second optical-signal filtering unit. The first optical-signal filtering circuit is configured to filter out a first interference pulse of the reflected light, wherein the first interference pulse has a first interference voltage value higher than a reference voltage. The second optical-signal filtering circuit is coupled to the first optical-signal filtering circuit and configured to generate a clock signal comprising a clock pulse; and filter out a second interference pulse that does not match the clock pulse in time point from the reflected light.Type: ApplicationFiled: November 30, 2022Publication date: March 7, 2024Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chih-Chun CHEN, Yi-Chi LEE, Chia-Yu HU, Ji-Bin HORNG
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Patent number: 11923237Abstract: A manufacturing method of a semiconductor device includes at least the following steps. A sacrificial substrate is provided. An epitaxial layer is formed on the sacrificial substrate. An etch stop layer is formed on the epitaxial layer. Carbon atoms are implanted into the etch stop layer. A capping layer and a device layer are formed on the etch stop layer. A handle substrate is bonded to the device layer. The sacrificial substrate, the epitaxial layer, and the etch stop layer having the carbon atoms are removed from the handle substrate.Type: GrantFiled: August 30, 2021Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Ming Chen, Kuei-Ming Chen, Po-Chun Liu, Chung-Yi Yu, Chia-Shiung Tsai
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Patent number: D1027976Type: GrantFiled: May 24, 2021Date of Patent: May 21, 2024Assignee: VIVOTEK INC.Inventors: Kuan-Hung Chen, Kai-Sheng Chuang, Chia-Chi Chang, Yu-Fang Huang, Kai-Ting Yu, Wen-Chun Chen, Shu-Jung Hsu, Tsao-Wei Hung