Patents by Inventor Chiahsun Tseng
Chiahsun Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10566454Abstract: Self-aligned contacts of a semiconductor device are fabricated by forming a metal gate structure on a portion of a semiconductor layer of a substrate. The metal gate structure contacts inner sidewalls of a gate spacer. A second sacrificial epitaxial layer is formed on a first sacrificial epitaxial layer. The first sacrificial epitaxial layer is adjacent to the gate spacer and is formed on source/drain regions of the semiconductor layer. The first and second sacrificial epitaxial layers are recessed. The recessing exposes at least a portion of the source/drain regions. A first dielectric layer is formed on the exposed portions of the source/drain regions, and over the gate spacer and metal gate structure. At least one cavity within the first dielectric layer is formed above at least one of the exposed portions of source/drain regions. At least one metal contact is formed within the at least one cavity.Type: GrantFiled: July 11, 2018Date of Patent: February 18, 2020Assignee: International Business Machines CorporationInventors: Hong He, Chiahsun Tseng, Chun-chen Yeh, Yunpeng Yin
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Patent number: 10529858Abstract: A semiconductor device comprises an insulation layer, an active semiconductor layer formed on an upper surface of the insulation layer, and a plurality of fins formed on the insulation layer. The fins are formed in the gate and spacer regions between a first source/drain region and second source/drain region, without extending into the first and second source/drain regions.Type: GrantFiled: March 6, 2018Date of Patent: January 7, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Hong He, Chiahsun Tseng, Junli Wang, Chun-chen Yeh, Yunpeng Yin
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Publication number: 20190206864Abstract: A process for etching a bulk integrated circuit substrate to form features on the substrate, such as fins, having substantially vertical walls comprises forming an etch stop layer beneath the surface of the substrate by ion implantation, e.g., carbon, oxygen, or boron ions or combinations thereof, masking the surface with a patterned etching mask that defines the features by openings in the mask to produce a masked substrate and etching the masked substrate to a level of the etch stop layer to form the features. In silicon substrates, ion implantation takes place along a silicon crystalline lattice beneath the surface of the substrate. The etchant comprises a halogen material that etches undoped silicon faster than the implants-rich silicon layer. This produces a circuit where the fins do not taper away from the vertical where they meet the substrate, and corresponding products and articles of manufacture having these features.Type: ApplicationFiled: February 11, 2019Publication date: July 4, 2019Applicant: International Business Machines CorporationInventors: Hong He, Siva Kanakasabapathy, Yunpeng Yin, Chiahsun Tseng, Junli Wang
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Patent number: 10217696Abstract: A first photoresist layer is patterned with a first pattern that includes an opening in a region between areas of two adjacent via holes to be formed. The opening in the first photoresist is transferred into a template layer to form a line trench therein. The lateral dimension of the trench is reduced by depositing a contiguous spacer layer that does not fill the trench completely. An etch-resistant material layer is conformally deposited and fills the trench, and is subsequently recessed to form an etch-resistant material portion filling the trench. A second photoresist layer is applied and patterned with a second pattern, which includes an opening that includes areas of two via holes and an area therebetween. A composite pattern of an intersection of the second pattern and the complement of the pattern of the etch-resistant material portion is transferred through the template layer.Type: GrantFiled: November 13, 2017Date of Patent: February 26, 2019Assignee: International Business Machines CorporationInventors: Chiahsun Tseng, Jin Liu, Lei Zhuang
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Patent number: 10170327Abstract: Methods and structures for fabricating fins for multigate devices are disclosed. In accordance with one method, a plurality of sidewalls are formed in or on a plurality of mandrels over a semiconductor substrate such that each of the mandrels includes a first sidewall composed of a first material and a second sidewall composed of a second material that is different from the first material. The first sidewall of a first mandrel of the plurality of mandrels is selectively removed. In addition, a pattern composed of remaining sidewalls of the plurality of sidewalls is transferred onto an underlying layer to form a hard mask in the underlying layer. Further, the fins are formed by employing the hard mask and etching semiconducting material in the substrate.Type: GrantFiled: June 5, 2017Date of Patent: January 1, 2019Assignee: International Business Machines CorporationInventors: Hong He, Chiahsun Tseng, Chun-Chen Yeh, Yunpeng Yin
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Patent number: 10170471Abstract: A semiconductor device, having a heterogeneous silicon stack, wherein the heterogeneous silicon stack comprises at least a base layer, a doped silicon layer, and an undoped silicon layer. The semiconductor device further includes a plurality of silicon fins atop a doped silicon oxide fin layer and an undoped silicon oxide fin layer, wherein the plurality of silicon fins have a uniform width along the height of the plurality of silicon fins, and wherein the plurality of silicon fins have a plurality of hard mask caps.Type: GrantFiled: October 13, 2016Date of Patent: January 1, 2019Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Hong He, Sivananda K. Kanakasabapathy, Chiahsun Tseng, Yunpeng Yin
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Publication number: 20180331039Abstract: Self-aligned contacts of a semiconductor device are fabricated by forming a metal gate structure on a portion of a semiconductor layer of a substrate. The metal gate structure contacts inner sidewalls of a gate spacer. A second sacrificial epitaxial layer is formed on a first sacrificial epitaxial layer. The first sacrificial epitaxial layer is adjacent to the gate spacer and is formed on source/drain regions of the semiconductor layer. The first and second sacrificial epitaxial layers are recessed. The recessing exposes at least a portion of the source/drain regions. A first dielectric layer is formed on the exposed portions of the source/drain regions, and over the gate spacer and metal gate structure. At least one cavity within the first dielectric layer is formed above at least one of the exposed portions of source/drain regions. At least one metal contact is formed within the at least one cavity.Type: ApplicationFiled: July 11, 2018Publication date: November 15, 2018Inventors: Hong HE, Chiahsun TSENG, Chun-chen YEH, Yunpeng YIN
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Patent number: 10037944Abstract: Self-aligned contacts of a semiconductor device are fabricated by forming a metal gate structure on a portion of a semiconductor layer of a substrate. The metal gate structure contacts inner sidewalls of a gate spacer. A second sacrificial epitaxial layer is formed on a first sacrificial epitaxial layer. The first sacrificial epitaxial layer is adjacent to the gate spacer and is formed on source/drain regions of the semiconductor layer. The first and second sacrificial epitaxial layers are recessed. The recessing exposes at least a portion of the source/drain regions. A first dielectric layer is formed on the exposed portions of the source/drain regions, and over the gate spacer and metal gate structure. At least one cavity within the first dielectric layer is formed above at least one of the exposed portions of source/drain regions. At least one metal contact is formed within the at least one cavity.Type: GrantFiled: January 27, 2017Date of Patent: July 31, 2018Assignee: International Business Machines CorporationInventors: Hong He, Chiahsun Tseng, Chun-chen Yeh, Yunpeng Yin
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Publication number: 20180197980Abstract: A semiconductor device comprises an insulation layer, an active semiconductor layer formed on an upper surface of the insulation layer, and a plurality of fins formed on the insulation layer. The fins are formed in the gate and spacer regions between a first source/drain region and second source/drain region, without extending into the first and second source/drain regions.Type: ApplicationFiled: March 6, 2018Publication date: July 12, 2018Inventors: Hong He, Chiahsun Tseng, Junli Wang, Chun-chen Yeh, Yunpeng Yin
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Patent number: 10020303Abstract: Methods for forming semiconductor devices having non-merged fin extensions. Methods for forming semiconductor devices include forming trenches in an insulator layer of a substrate. Fins are formed in the trenches and a dummy gate is formed over the fins, leaving a source and drain region exposed. The fins are etched below a surface level of a surrounding insulator layer. Fin extensions are epitaxially grown from the etched fins.Type: GrantFiled: March 24, 2015Date of Patent: July 10, 2018Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, RENESAS ELECTRONICS CORPORATIONInventors: Hong He, Shogo Mochizuki, Chiahsun Tseng, Chun-Chen Yeh, Yunpeng Yin
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Patent number: 9997367Abstract: A metal layer is deposited over an underlying material layer. The metal layer includes an elemental metal that can be converted into a dielectric metal-containing compound by plasma oxidation and/or nitridation. A hard mask portion is formed over the metal layer. Plasma oxidation or nitridation is performed to convert physically exposed surfaces of the metal layer into the dielectric metal-containing compound. The sequence of a surface pull back of the hard mask portion, trench etching, another surface pull back, and conversion of top surfaces into the dielectric metal-containing compound are repeated to form a line pattern having a spacing that is not limited by lithographic minimum dimensions.Type: GrantFiled: July 18, 2016Date of Patent: June 12, 2018Assignee: International Business Machines CorporationInventors: Chiahsun Tseng, David V. Horak, Chun-chen Yeh, Yunpeng Yin
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Patent number: 9991255Abstract: Semiconductor devices having non-merged fin extensions. A semiconductor device includes fins formed in trenches in an insulator layer, each of the fins having a uniform crystal orientation and a fin cap in a source and drain region that extends vertically and laterally beyond the trench. The fin caps of the respective fins are separate from one another.Type: GrantFiled: March 18, 2015Date of Patent: June 5, 2018Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, RENESAS ELECTRONICS CORPORATIONInventors: Hong He, Shogo Mochizuki, Chiahsun Tseng, Chun-Chen Yeh, Yunpeng Yin
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Patent number: 9991258Abstract: Semiconductor devices include multiple fins formed in trenches in an insulator layer. Each of the plurality of fins has a uniform crystal orientation and a fin cap in a source and drain region that extends vertically and laterally beyond the trench. The fin caps of the respective fins are separate from one another. A gate structure is formed over the fins that leaves the source and drain regions exposed. The insulator layer at least partially covers a sidewall of the gate structure.Type: GrantFiled: October 13, 2016Date of Patent: June 5, 2018Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, RENESAS ELECTRONICS CORPORATIONInventors: Hong He, Shogo Mochizuki, Chiahsun Tseng, Chun-Chen Yeh, Yunpeng Yin
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Patent number: 9985030Abstract: A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A cladding layer is epitaxially grown on a portion of the at least one semiconductor fin. The cladding layer is oxidized such that r such that ions are condensed therefrom and are diffused into the at least one semiconductor fin while the cladding layer is converted to an oxide layer. The oxide layer is removed to expose the at least one semiconductor fin having a diffused fin portion that enhances electron hole mobility therethrough.Type: GrantFiled: December 23, 2014Date of Patent: May 29, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Hong He, Ali Khakifirooz, Chiahsun Tseng, Chun-chen Yeh, Yunpeng Yin
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Patent number: 9947791Abstract: A semiconductor device comprises an insulation layer, an active semiconductor layer formed on an upper surface of the insulation layer, and a plurality of fins formed on the insulation layer. The fins are formed in the gate and spacer regions between a first source/drain region and second source/drain region, without extending into the first and second source/drain regions.Type: GrantFiled: August 13, 2013Date of Patent: April 17, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Hong He, Chiahsun Tseng, Junli Wang, Chun-chen Yeh, Yunpeg Yin
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Patent number: 9941191Abstract: A first photoresist layer is patterned with a first pattern that includes an opening in a region between areas of two adjacent via holes to be formed. The opening in the first photoresist is transferred into a template layer to form a line trench therein. The lateral dimension of the trench is reduced by depositing a contiguous spacer layer that does not fill the trench completely. An etch-resistant material layer is conformally deposited and fills the trench, and is subsequently recessed to form an etch-resistant material portion filling the trench. A second photoresist layer is applied and patterned with a second pattern, which includes an opening that includes areas of two via holes and an area therebetween. A composite pattern of an intersection of the second pattern and the complement of the pattern of the etch-resistant material portion is transferred through the template layer.Type: GrantFiled: October 15, 2015Date of Patent: April 10, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chiahsun Tseng, Jin Liu, Lei Zhuang
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Publication number: 20180068929Abstract: A first photoresist layer is patterned with a first pattern that includes an opening in a region between areas of two adjacent via holes to be formed. The opening in the first photoresist is transferred into a template layer to form a line trench therein. The lateral dimension of the trench is reduced by depositing a contiguous spacer layer that does not fill the trench completely. An etch-resistant material layer is conformally deposited and fills the trench, and is subsequently recessed to form an etch-resistant material portion filling the trench. A second photoresist layer is applied and patterned with a second pattern, which includes an opening that includes areas of two via holes and an area therebetween. A composite pattern of an intersection of the second pattern and the complement of the pattern of the etch-resistant material portion is transferred through the template layer.Type: ApplicationFiled: November 13, 2017Publication date: March 8, 2018Inventors: Chiahsun Tseng, Jin Liu, Lei Zhuang
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Publication number: 20170271167Abstract: Methods and structures for fabricating fins for multigate devices are disclosed. In accordance with one method, a plurality of sidewalls are formed in or on a plurality of mandrels over a semiconductor substrate such that each of the mandrels includes a first sidewall composed of a first material and a second sidewall composed of a second material that is different from the first material. The first sidewall of a first mandrel of the plurality of mandrels is selectively removed. In addition, a pattern composed of remaining sidewalls of the plurality of sidewalls is transferred onto an underlying layer to form a hard mask in the underlying layer. Further, the fins are formed by employing the hard mask and etching semiconducting material in the substrate.Type: ApplicationFiled: June 5, 2017Publication date: September 21, 2017Inventors: Hong He, Chiahsun Tseng, Chun-Chen Yeh, Yunpeng Yin
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Patent number: 9728419Abstract: Methods and structures for fabricating fins for multigate devices are disclosed. In accordance with one method, a plurality of sidewalls are formed in or on a plurality of mandrels over a semiconductor substrate such that each of the mandrels includes a first sidewall composed of a first material and a second sidewall composed of a second material that is different from the first material. The first sidewall of a first mandrel of the plurality of mandrels is selectively removed. In addition, a pattern composed of remaining sidewalls of the plurality of sidewalls is transferred onto an underlying layer to form a hard mask in the underlying layer. Further, the fins are formed by employing the hard mask and etching semiconducting material in the substrate.Type: GrantFiled: April 27, 2015Date of Patent: August 8, 2017Assignee: International Business Machines CorporationInventors: Hong He, Chiahsun Tseng, Chun-Chen Yeh, Yunpeng Yin
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Patent number: 9728534Abstract: A method of forming a fin-based field-effect transistor device includes forming one or more first fins comprising silicon on a substrate, forming epitaxial layers on sides of the one or more first fins, and removing the one or more first fins to form a plurality of second fins.Type: GrantFiled: October 7, 2015Date of Patent: August 8, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hong He, Chiahsun Tseng, Chun-Chen Yeh, Yunpeng Yin