Patents by Inventor Chiaki Shinagawa
Chiaki Shinagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8032783Abstract: The service life of memory cards is to be substantially elongated against the occurrence of faulty blocks. A control logic searches blocks in a nonvolatile memory cell array for any acquired fault on the basis of a fault-inviting code in a management information section. If any faulty block is detected, the faulty block will be subjected to write/read comparison of data to judge whether or not the data in the block are normal. Any block determined to be normal will undergo rewriting of its fault-inviting code and registered as a normal block. Further, the registered block is stored into a write management table in the management area as a writable block. This enables an essentially normal block judged faulty on account of an erratic error or some other reason to be restored.Type: GrantFiled: September 10, 2008Date of Patent: October 4, 2011Assignee: Renesas Electronics CorporationInventors: Shinsuke Asari, Chiaki Shinagawa, Yasuhiro Nakamura, Motoki Kanamori, Atsushi Shiraishi
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Publication number: 20090019210Abstract: The service life of memory cards is to be substantially elongated against the occurrence of faulty blocks. A control logic searches blocks in a nonvolatile memory cell array for any acquired fault on the basis of a fault-inviting code in a management information section. If any faulty block is detected, the faulty block will be subjected to write/read comparison of data to judge whether or not the data in the block are normal. Any block determined to be normal will undergo rewriting of its fault-inviting code and registered as a normal block. Further, the registered block is stored into a write management table in the management area as a writable block. This enables an essentially normal block judged faulty on account of an erratic error or some other reason to be restored.Type: ApplicationFiled: September 10, 2008Publication date: January 15, 2009Inventors: Shinsuke Asari, Chiaki Shinagawa, Yasuhiro Nakamura, Motoki Kanamori, Atsushi Shiraishi
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Patent number: 7451266Abstract: A risk of data garbling due to cumulative impact of disturbances occurring in memory areas in which no rewrite occurs is to be prevented. A memory device has an erasable and writable nonvolatile memory and a control circuit, wherein the control circuit is enabled to perform processing at a prescribed timing to replace memory areas. The replacement processing is accomplished by writing stored data in a first memory area in which rewriting is relatively infrequent into an unused second memory area, and making the second memory area into which the writing has been done a used area in place of the first memory area. Since this replacement processing is intended to replace memory areas in which rewriting is infrequent with other memory areas as described above, it is possible to prevent the risk of data garbling due to the cumulative impact of disturbances occurring in memory areas in which no rewrite occurs.Type: GrantFiled: March 19, 2007Date of Patent: November 11, 2008Assignee: Renesas Technology Corp.Inventors: Chiaki Shinagawa, Atsushi Shiraishi, Motoki Kanamori
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Patent number: 7437602Abstract: The service life of memory cards is to be substantially elongated against the occurrence of faulty blocks. A control logic searches blocks in a nonvolatile memory cell array for any acquired fault on the basis of a fault-inviting code in a management information section. If any faulty block is detected, the faulty block will be subjected to write/read comparison of data to judge whether or not the data in the block are normal. Any block determined to be normal will undergo rewriting of its fault-inviting code and registered as a normal block. Further, the registered block is stored into a write management table in the management area as a writable block. This enables an essentially normal block judged faulty on account of an erratic error or some other reason to be restored.Type: GrantFiled: March 15, 2005Date of Patent: October 14, 2008Assignee: Renesas Technology Corp.Inventors: Shinsuke Asari, Chiaki Shinagawa, Yasuhiro Nakamura, Motoki Kanamori, Atsushi Shiraishi
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Publication number: 20070186033Abstract: A risk of data garbling due to cumulative impact of disturbances occurring in memory areas in which no rewrite occurs is to be prevented. A memory device has an erasable and writable nonvolatile memory and a control circuit, wherein the control circuit is enabled to perform processing at a prescribed timing to replace memory areas. The replacement processing is accomplished by writing stored data in a first memory area in which rewriting is relatively infrequent into an unused second memory area, and making the second memory area into which the writing has been done a used area in place of the first memory area. Since this replacement processing is intended to replace memory areas in which rewriting is infrequent with other memory areas as described above, it is possible to prevent the risk of data garbling due to the cumulative impact of disturbances occurring in memory areas in which no rewrite occurs.Type: ApplicationFiled: March 19, 2007Publication date: August 9, 2007Inventors: Chiaki Shinagawa, Atsushi Shiraishi, Motoki Kanamori
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Patent number: 7061812Abstract: Disclosed is a memory card which ensures high-speed data writing operations. The memory card is formed of an erasable and programmable nonvolatile memory and a control circuit. A memory array of the nonvolatile memory has an erasing table including a first flag designating whether a memory area is a vacant area or not in every erasing unit. The control circuit exercises, when the number of memory areas in which the erasable data is written becomes a constant value, pre-erasing control to previously erase the erasable data over the memory area depending on the first flag indicating a vacant area. Since the erasing process is previously executed to the vacant memory area, necessity for insertion of the erasing process just before the writing process using the vacant memory area can be reduced and thereby writing data to the memory card can be highly speeded.Type: GrantFiled: April 2, 2004Date of Patent: June 13, 2006Assignee: Renesas Technology Corp.Inventors: Chiaki Shinagawa, Motoki Kanamori, Atsushi Shiraishi
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Publication number: 20050232037Abstract: The service life of memory cards is to be substantially elongated against the occurrence of faulty blocks. A control logic searches blocks in a nonvolatile memory cell array for any acquired fault on the basis of a fault-inviting code in a management information section. If any faulty block is detected, the faulty block will be subjected to write/read comparison of data to judge whether or not the data in the block are normal. Any block determined to be normal will undergo rewriting of its fault-inviting code and registered as a normal block. Further, the registered block is stored into a write management table in the management area as a writable block. This enables an essentially normal block judged faulty on account of an erratic error or some other reason to be restored.Type: ApplicationFiled: March 15, 2005Publication date: October 20, 2005Inventors: Shinsuke Asari, Chiaki Shinagawa, Yasuhiro Nakamura, Motoki Kanamori, Atsushi Shiraishi
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Publication number: 20040202024Abstract: Disclosed is a memory card which ensures high-speed data writing operations. The memory card is formed of an erasable and programmable nonvolatile memory and a control circuit. A memory array of the nonvolatile memory has an erasing table including a first flag designating whether a memory area is a vacant area or not in every erasing unit. The control circuit exercises, when the number of memory areas in which the erasable data is written becomes a constant value, pre-erasing control to previously erase the erasable data over the memory area depending on the first flag indicating a vacant area. Since the erasing process is previously executed to the vacant memory area, necessity for insertion of the erasing process just before the writing process using the vacant memory area can be reduced and thereby writing data to the memory card can be highly speeded.Type: ApplicationFiled: April 2, 2004Publication date: October 14, 2004Applicant: Renesas Technology Corp.Inventors: Chiaki Shinagawa, Motoki Kanamori, Atsushi Shiraishi
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Publication number: 20040205290Abstract: A risk of data garbling due to cumulative impact of disturbances occurring in memory areas in which no rewrite occurs is to be prevented. A memory device has an erasable and writable nonvolatile memory and a control circuit, wherein the control circuit is enabled to perform processing at a prescribed timing to replace memory areas. The replacement processing is accomplished by writing stored data in a first memory area in which rewriting is relatively infrequent into an unused second memory area, and making the second memory area into which the writing has been done a used area in place of the first memory area. Since this replacement processing is intended to replace memory areas in which rewriting is infrequent with other memory areas as described above, it is possible to prevent the risk of data garbling due to the cumulative impact of disturbances occurring in memory areas in which no rewrite occurs.Type: ApplicationFiled: March 26, 2004Publication date: October 14, 2004Applicant: Renesas Technology Corp.Inventors: Chiaki Shinagawa, Atsushi Shiraishi, Motoki Kanamori