Abstract: Present invention provides an innovative alloy formation method for a solid state battery and the sold state battery thereof. The said sulfide solid-state electrolyte is doped with anode-philic material to replace the cation ion when synthesizing the sulfide solid-state electrolyte to improve its ionic conductivity but reduce the electronic conductivity avoiding internal electricity leakage. The present invention can also increase the moisture resistance for the sulfide solid-state electrolyte. After performing life cycles, an alloy is formed on an interface of the sulfide solid-state electrolyte which could stabilize and prolongs the life cycles of the full battery.

Abstract: The present invention provides a method for stabilizing an electrode using a functional layer, the electrode and applications thereof, which generates a beneficial electrolyte interface layer on the surface of the negative electrode after charging and discharging, and a protective buffer layer to form an alloy that facilitates the deposition of dense lithium on the negative current collector, significantly extending the life of the battery.

Abstract: The present disclosure is directed to imaging LiDARs with separate transmit (Tx) and receive (Rx) optical antennas fed by different optical waveguides. This pair of optical antennas can be activated at the same time through a dual-channel optical switch network, with the Tx antenna connected to a laser source and the Rx antenna connected to a receiver. The Tx and Rx antennas can be positioned adjacent to each other, so they point to approximately the same far-field angle. No optical alignment between the Tx and Rx is necessary. This LiDAR configuration, referred to herein as pseudo-monostatic LiDAR, eliminates spurious reflections and increases the dynamic range of the LiDAR.

Abstract: A large-scale single-photonics-based optical switching system that occupies an area larger than the maximum area of a standard step-and-repeat lithography reticle is disclosed. The system includes a plurality of identical switch blocks, each of is formed in a different reticle field that no larger than the maximum reticle size. Bus waveguides of laterally adjacent switch blocks are stitched together at lateral interfaces that include a second arrangement of waveguide ports that is common to all lateral interfaces. Bus waveguides of vertically adjacent switch blocks are stitched together at vertical interfaces that include a first arrangement of waveguide ports that is common to all vertical interfaces. In some embodiments, the lateral and vertical interfaces include waveguide ports having waveguide coupling regions that are configured to mitigate optical loss due to stitching error.

Abstract: Embodiments of the present disclosure relate to an electrostatic protection structure and an electrostatic protection circuit. The electrostatic protection structure includes: a SCR structure and a trigger structure; the SCR structure includes: a well region of a second conductivity type and a first well of a first conductivity type region, a first-doped region of the first conductivity type, and a first-doped region of the second conductivity type; the trigger structure includes: a first-doped region of the second conductivity type, a second well region of the first conductivity type, a second-doped region of two conductivity types, a third-doped region of the second conductivity type, a fourth-doped region of the second conductivity type, and a first gate electrode.

Abstract: A package structure includes a conductive feature structure, a die, an adhesive layer, an insulator, a through via, and an encapsulant. The die is disposed over the conductive feature structure. The adhesive layer is disposed below the die. The insulator is disposed between the adhesive layer and a polymer layer of the conductive feature structure. The through via extends through the insulator to connect to the conductive feature structure. The encapsulant is disposed on the insulator and the conductive feature structure, laterally encapsulating the die and the through via, and between the through via and the insulator. The insulator has a coefficient of thermal expansion less than a coefficient of thermal expansion of the encapsulant.

Abstract: A semiconductor device includes a first set of nanostructures stacked over a substrate in a vertical direction, and each of the first set of nanostructures includes a first end portion and a second end portion, and a first middle portion laterally between the first end portion and the second end portion. The first end portion and the second end portion are thicker than the first middle portion. The semiconductor device also includes a first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures, and a gate structure around the first plurality of semiconductor capping layers.

Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.

Abstract: The present disclosure provides a semiconductor structure with having a source/drain feature with a central cavity, and a source/drain contact feature formed in central cavity of the source/drain region, wherein the source/drain contact feature is nearly wrapped around by the source/drain region. The source/drain contact feature may extend to a lower most of a plurality semiconductor layers.

Abstract: A data processing method based on Trojan circuit detection includes controlling a processor, in a testing stage, to perform following steps: obtaining a plurality of characteristic values corresponding to a logic gate circuit; performing a distribution adjustment operation on the characteristic values to generate a plurality of adjusted characteristic values; and performing classification on the adjusted characteristic values to generate a logic identification result.

Abstract: A data processing circuit and a fault-mitigating method are provided. In the method, multiple sub-sequences are divided from sequence data. A first sub-sequence of the sub-sequences is accessed from a memory for a multiply-accumulate (MAC) operation to obtain a first computed result. The MAC operation is performed on a second sub-sequence of the sub-sequences in the memory to obtain a second computed result. The first and the second computed results are combined, where the combined result of the first and the second computed results is related to the result of the MAC operation on the sequence data directly. Accordingly, the error rate could be reduced, so as to mitigate fault.

Abstract: A data processing circuit and a fault mitigating method are provided. The method is adapted for a memory having at least one fault bit. The memory provides a block for data storage. A difference between an output of a value of a plurality of bits input to at least one computing layer in a neural network and a correct value is determined. The bits are respectively considered the at least one fault bit. A repair condition is determined based on the difference. The repair condition includes a correspondence between a position where the fault bit is located in the block and at least one non-fault bit in the memory. A value of at least one non-fault bit of the memory replaces a value of the fault bit based on the repair condition.

Abstract: A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.

Abstract: A package structure including a semiconductor die, a redistribution layer, a plurality of antenna patterns, a die attach film, and an insulating encapsulant is provided. The semiconductor die have an active surface and a backside surface opposite to the active surface. The redistribution layer is located on the active surface of the semiconductor die and electrically connected to the semiconductor die. The antenna patterns are located over the backside surface of the semiconductor die. The die attach film is located in between the semiconductor die and the antenna patterns, wherein the die attach film includes a plurality of fillers, and an average height of the die attach film is substantially equal to an average diameter of the plurality of fillers. The insulating encapsulant is located in between the redistribution layer and the antenna patterns, wherein the insulating encapsulant encapsulates the semiconductor die and the die attach film.

Abstract: A method includes depositing a first work-function layer and a second work-function layer in a first device region and a second device region, respectively, and depositing a first fluorine-blocking layer and a second fluorine-blocking layer in the first device region and the second device region, respectively. The first fluorine-blocking layer is over the first work-function layer, and the second fluorine-blocking layer is over the second work-function layer. The method further includes removing the second fluorine-blocking layer, and forming a first metal-filling layer over the first fluorine-blocking layer, and a second metal-filling layer over the second work-function layer.

Abstract: An image sensor is provided. The image sensor includes a substrate and isolation structures disposed on the substrate. The isolation structures are electrically non-conductive and define pixel regions. The image sensor also includes electrodes disposed on the substrate and in direct contact with the isolation structures. The image sensor further includes an active layer disposed between the isolation structures. Moreover, the image sensor includes an encapsulation layer disposed over the active layer. The image sensor also includes a color filter layer disposed over the encapsulation layer.

Abstract: A device includes a first package connected to an interconnect substrate, wherein the interconnect substrate includes conductive routing; and a second package connected to the interconnect substrate, wherein the second package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler and to a photodetector; a via extending through the substrate; an interconnect structure over the photonic layer, wherein the interconnect structure is connected to the photodetector and to the via; and an electronic die bonded to the interconnect structure, wherein the electronic die is connected to the interconnect structure.

Abstract: The present disclosure relates to a system, a method and a computer-readable medium for rendering a streaming on a user terminal. The method includes rendering the streaming in a first mode, receiving an environment parameter of the user terminal, receiving a timing when the user terminal closes the streaming, determining a threshold value of the environment parameter based on the timing the user terminal closes the streaming, receiving an updated environment parameter of the user terminal, and rendering the streaming in a second mode if the updated environment parameter meets the threshold value. The second mode includes fewer data objects than the first mode or includes a downgraded version of a data object in the first mode for the rendering. The present disclosure can customize the rendering mode for each user and maximize the satisfaction of viewing streaming for each user.

Abstract: Semiconductor device structures having gate structures with tunable threshold voltages are provided. Various geometries of device structure can be varied to tune the threshold voltages. In some examples, distances from tops of fins to tops of gate structures can be varied to tune threshold voltages. In some examples, distances from outermost sidewalls of gate structures to respective nearest sidewalls of nearest fins to the respective outermost sidewalls (which respective gate structure overlies the nearest fin) can be varied to tune threshold voltages.

Abstract: An optical engine module including at least two laser sources, collimators, a light combining lens group, an aperture, a beam shaping lens group, a MEMS scanning module, and a beam expansion lens group is provided. The at least two laser sources respectively generate at least two laser beams with different wavelengths. The collimators respectively collimate the at least two laser beams to generate at least two collimated beams. The light combining lens group combines the at least two collimated beams into a combined beam. The aperture filters stray beams of the combined beam. The beam shaping lens group shapes the combined beam to generate a shaped beam with a perfect circle. The MEMS scanning module reflects the shaped beam and scans in horizontal and vertical directions to form a scanning beam. The beam expansion lens group expands the scanning beam into an expanded beam having a predetermined area.