Abstract: A new method to polish down conductive lines in the manufacture of an integrated circuit device is achieved. The method comprises providing a plurality of conductive lines overlying a substrate. A high density plasma (HDP) oxide layer is deposited overlying the substrate and the conductive lines. In the regions between the conductive lines, first planar surfaces of the HDP oxide layer are formed below the top of the conductive lines. The HDP oxide layer is sputtered down overlying the conductive lines such that second planar surfaces of the HDP oxide layer are formed above the conductive lines. A polish stopping layer is deposited overlying the HDP oxide layer. A film layer is deposited overlying the polish stopping layer. The film layer is polished down to the polish stopping layer overlying the second planar top surfaces.

Abstract: A booster power management integrated circuit chip includes first and second output pads, a transistor switch coupled between the first and second output pads and having a gate, and a trigger circuit coupled between the first and second output pads and further coupled to the gate of the transistor switch. The trigger circuit drives the transistor switch to conduct when an instantaneous voltage larger than a trigger voltage level is present between the first and second output pads so as to enable electric current to flow through the transistor switch.

Abstract: A new method to polish down conductive lines in the manufacture of an integrated circuit device is achieved. The method comprises providing a plurality of conductive lines overlying a substrate. A high density plasma (HDP) oxide layer is deposited overlying the substrate and the conductive lines. In the regions between the conductive lines, first planar surfaces of the HDP oxide layer are formed below the top of the conductive lines. The HDP oxide layer is sputtered down overlying the conductive lines such that second planar surfaces of the HDP oxide layer are formed above the conductive lines. A polish stopping layer is deposited overlying the HDP oxide layer. A film layer is deposited overlying the polish stopping layer. The film layer is polished down to the polish stopping layer overlying the second planar top surfaces.

Abstract: A booster power management integrated circuit chip includes first and second output pads, a transistor switch coupled between the first and second output pads and having a gate, and a trigger circuit coupled between the first and second output pads and further coupled to the gate of the transistor switch. The trigger circuit drives the transistor switch to conduct when an instantaneous voltage larger than a trigger voltage level is present between the first and second output pads so as to enable electric current to flow through the transistor switch.

Abstract: A new method to polish down conductive lines in the manufacture of an integrated circuit device is achieved. The method comprises providing a plurality of conductive lines overlying a substrate. A high density plasma (HDP) oxide layer is deposited overlying the substrate and the conductive lines. In the regions between the conductive lines, first planar surfaces of the HDP oxide layer are formed below the top of the conductive lines. The HDP oxide layer is sputtered down overlying the conductive lines such that second planar surfaces of the HDP oxide layer are formed above the conductive lines. A polish stopping layer is deposited overlying the HDP oxide layer. A film layer is deposited overlying the polish stopping layer. The film layer is polished down to the polish stopping layer overlying the second planar top surfaces.

Abstract: A cellular MOS array becomes denser by employing an asymmetric structure, in which the areas of the sources are reduced without changing the length and the width of the channel thereof, and thereby the chip size is reduced and the cost is lowered.

Abstract: A new method to polish down conductive lines in the manufacture of an integrated circuit device is achieved. The method comprises providing a plurality of conductive lines overlying a substrate. A high density plasma (HDP) oxide layer is deposited overlying the substrate and the conductive lines. In the regions between the conductive lines, first planar surfaces of the HDP oxide layer are formed below the top of the conductive lines. The HDP oxide layer is sputtered down overlying the conductive lines such that second planar surfaces of the HDP oxide layer are formed above the conductive lines. A polish stopping layer is deposited overlying the HDP oxide layer. A film layer is deposited overlying the polish stopping layer. The film layer is polished down to the polish stopping layer overlying the second planar top surfaces.

Abstract: A cellular MOS array becomes denser by employing an asymmetric structure, in which the areas of the sources are reduced without changing the length and the width of the channel thereof, and thereby the chip size is reduced and the cost is lowered.