Patents by Inventor Chiao-Ling Lung
Chiao-Ling Lung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9177940Abstract: A fault-tolerant unit and a fault-tolerant method for through-silicon via (TSV) are provided. The fault-tolerant unit includes TSV structures TSV1˜TSVn, nodes N11˜N1n, nodes N21˜N2n and a switching module. The TSV structure TSVi is connected between the node N1i of the first chip and the node N2i of the second chip, wherein 1?i?n. The switching module is connected between the nodes N21˜N2n of the second chip and a test path of the second chip. In normal operation state, the switching module disconnects the test path and the nodes N21˜N2n when the TSV structures TSV1˜TSVn are valid. The switching module connects the node N2i to at least another one of the nodes N21˜N2n when the TSV structure TSVi is faulty in the normal operation state. In test status, the switching module connects the test path to the nodes N21˜N2n.Type: GrantFiled: September 20, 2011Date of Patent: November 3, 2015Assignee: Industrial Technology Research InstituteInventors: Chiao-Ling Lung, Yu-Shih Su, Shih-Chieh Chang, Yiyu Shi
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Patent number: 9048342Abstract: A semiconductor device stacked structure is disclosed, which includes multiple semiconductor devices and at least one reinforcing structure. The semiconductor devices are stacked on one another. At least one semiconductor device has at least one through silicon via. Each reinforcing structure surrounds a corresponding one of the at least one through silicon via and is electrically insulated from the semiconductor devices. The at least one reinforcing structure includes multiple reinforcing elements and at least one connecting element. Each reinforcing element is disposed between the semiconductor devices. Vertical projections of the reinforcing elements on a plane define a close region, and a projection of the at least one through silicon via on the plane is located within the close region. The connecting element is located in an overlapping region of the vertical projections of the reinforcing elements on the plane, for connecting the reinforcing elements to form the reinforcing structure.Type: GrantFiled: April 19, 2012Date of Patent: June 2, 2015Assignee: Industrial Technology Research InstituteInventors: Ding-Ming Kwai, Yung-Fa Chou, Chiao-Ling Lung, Jui-Hung Chien
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Patent number: 8912448Abstract: A stress relief structure is provided. The stress relief structure includes a stress relief body, at least one first stress relief base and at least one second stress relief base. The stress relief body has an upper surface and a lower surface opposite to each other. The first stress relief base is disposed on the upper surface of the stress relief body. The second stress relief base is disposed on the lower surface of the stress relief body. The at least one first stress relief base and the at least one second stress relief base are interlaced to each other.Type: GrantFiled: March 22, 2013Date of Patent: December 16, 2014Assignee: Industrial Technology Research InstituteInventors: Jui-Hung Chien, Chiao-Ling Lung
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Publication number: 20140151090Abstract: A stress relief structure is provided. The stress relief structure includes a stress relief body, at least one first stress relief base and at least one second stress relief base. The stress relief body has an upper surface and a lower surface opposite to each other. The first stress relief base is disposed on the upper surface of the stress relief body. The second stress relief base is disposed on the lower surface of the stress relief body. The at least one first stress relief base and the at least one second stress relief base are interlaced to each other.Type: ApplicationFiled: March 22, 2013Publication date: June 5, 2014Applicant: Industrial Technology Research InstituteInventors: Jui-Hung Chien, Chiao-Ling Lung
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Publication number: 20130161819Abstract: A semiconductor device stacked structure is disclosed, which includes multiple semiconductor devices and at least one reinforcing structure. The semiconductor devices are stacked on one another. At least one semiconductor device has at least one through silicon via. Each reinforcing structure surrounds a corresponding one of the at least one through silicon via and is electrically insulated from the semiconductor devices. The at least one reinforcing structure includes multiple reinforcing elements and at least one connecting element. Each reinforcing element is disposed between the semiconductor devices. Vertical projections of the reinforcing elements on a plane define a close region, and a projection of the at least one through silicon via on the plane is located within the close region. The connecting element is located in an overlapping region of the vertical projections of the reinforcing elements on the plane, for connecting the reinforcing elements to form the reinforcing structure.Type: ApplicationFiled: April 19, 2012Publication date: June 27, 2013Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Ding-Ming Kwai, Yung-Fa Chou, Chiao-Ling Lung, Jui-Hung Chien
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Publication number: 20120248438Abstract: A fault-tolerant unit and a fault-tolerant method for through-silicon via (TSV) are provided. The fault-tolerant unit includes TSV structures TSV1˜TSVn, nodes N11˜N1n, nodes N21˜N2n and a switching module. The TSV structure TSVi is connected between the node N11 of the first chip and the node N2i of the second chip, wherein 1?i?n. The switching module is connected between the nodes N21˜N2n of the second chip and a test path of the second chip. In normal operation state, the switching module disconnects the test path and the nodes N21˜N2n when the TSV structures TSV1˜TSVn are valid. The switching module connects the node N2i to at least another one of the nodes N21˜N2n when the TSV structure TSVi is faulty in the normal operation state. In test status, the switching module connects the test path to the nodes N21˜N2n.Type: ApplicationFiled: September 20, 2011Publication date: October 4, 2012Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chiao-Ling Lung, Yu-Shih Su, Shih-Chieh Chang, Yiyu Shi
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Patent number: 8179181Abstract: A power-mode-aware (PMA) clock tree and a synthesis method thereof are provided. The clock tree includes a sub clock tree and a PMA buffer. The sub clock tree transmits a delayed clock signal to a function module, wherein a power mode of the function module is determined according to a power information. The PMA buffer is coupled to the sub clock tree. The PMA buffer determines the delay time of a system clock signal according to the power information delays the system clock signal, and outputs the delayed system clock signal to the sub clock tree as the delayed clock signal.Type: GrantFiled: March 31, 2010Date of Patent: May 15, 2012Assignees: Industrial Technology Research Institute, National Tsing Hua UniversityInventors: Chiao-Ling Lung, Shih-Chieh Chang
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Publication number: 20110121875Abstract: A power-mode-aware (PMA) clock tree and a synthesis method thereof are provided. The clock tree includes a sub clock tree and a PMA buffer. The sub clock tree transmits a delayed clock signal to a function module, wherein a power mode of the function module is determined according to a power information. The PMA buffer is coupled to the sub clock tree. The PMA buffer determines the delay time of a system clock signal according to the power information delays the system clock signal, and outputs the delayed system clock signal to the sub clock tree as the delayed clock signal.Type: ApplicationFiled: March 31, 2010Publication date: May 26, 2011Applicants: Industrial Technology Research Institute, National Tsing Hua UniversityInventors: Chiao-Ling Lung, Shih-Chieh Chang