Patents by Inventor Chiao-Shun Chuang
Chiao-Shun Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240106432Abstract: An apparatus includes a capacitive device configured to provide bias power for a high-side switch, a gate drive path having variable resistance connected between the capacitive device and a gate of the high-side switch, wherein the gate drive path having variable resistance is of a first resistance value in response to a turn-on of the high-side switch, and the gate drive path having variable resistance is of a second resistance value in response to a turn-off of the high-side switch, and wherein the second resistance value is greater than the first resistance value, and a control switch connected between the gate of the high-side switch and ground.Type: ApplicationFiled: December 5, 2023Publication date: March 28, 2024Inventors: Chiao-Shun CHUANG, Ta-Chuan KUO, Ke-Horng CHEN
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Patent number: 11876511Abstract: An apparatus includes a capacitive device configured to provide bias power for a high-side switch, a gate drive path having variable resistance connected between the capacitive device and a gate of the high-side switch, wherein the gate drive path having variable resistance is of a first resistance value in response to a turn-on of the high-side switch, and the gate drive path having variable resistance is of a second resistance value in response to a turn-off of the high-side switch, and wherein the second resistance value is greater than the first resistance value, and a control switch connected between the gate of the high-side switch and ground.Type: GrantFiled: July 8, 2021Date of Patent: January 16, 2024Assignee: Diodes IncorporatedInventors: Chiao-Shun Chuang, Ta-Chuan Kuo, Ke-Horng Chen
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Patent number: 11749750Abstract: A split-gate trench device chip has an active region in which a plurality of active trenches are disposed. The active region is enclosed by termination trenches disposed in a termination region, which extends to the edges of the chip. A gate metal lead is disposed on the device surface. The gate metal lead makes contact to gate electrodes in the active trenches through contact holes disposed in the active region. A source or a drain metal lead is also disposed on the surface. The source or the drain metal lead makes contact to the field plate electrodes through contact holes disposed outside the active region. Each active trench in the active region has a first end merge into a first termination trench and a second end separated from an adjacent second termination trench.Type: GrantFiled: August 16, 2022Date of Patent: September 5, 2023Assignee: Diodes IncorporatedInventors: Chiao-Shun Chuang, Tsung-Wei Pai, Yun-Pu Ku
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Publication number: 20220320331Abstract: A split-gate trench device chip has an active region in which a plurality of active trenches are disposed. The active region is enclosed by termination trenches disposed in a termination region, which extends to the edges of the chip. A gate metal lead is disposed on the device surface. The gate metal lead makes contact to gate electrodes in the active trenches through contact holes disposed in the active region. A source or a drain metal lead is also disposed on the surface. The source or the drain metal lead makes contact to the field plate electrodes through contact holes disposed outside the active region. Each active trench in the active region has a first end merge into a first termination trench and a second end separated from an adjacent second termination trench.Type: ApplicationFiled: March 31, 2021Publication date: October 6, 2022Applicant: Diodes IncorporatedInventors: Chiao-Shun Chuang, Tsung-Wei Pai, Yun-Pu Ku
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Patent number: 11456379Abstract: A split-gate trench device chip has an active region in which a plurality of active trenches are disposed. The active region is enclosed by termination trenches disposed in a termination region, which extends to the edges of the chip. A gate metal lead is disposed on the device surface. The gate metal lead makes contact to gate electrodes in the active trenches through contact holes disposed in the active region. A source or a drain metal lead is also disposed on the surface. The source or the drain metal lead makes contact to the field plate electrodes through contact holes disposed outside the active region. Each active trench in the active region has a first end merge into a first termination trench and a second end separated from an adjacent second termination trench.Type: GrantFiled: March 31, 2021Date of Patent: September 27, 2022Assignee: Diodes IncorporatedInventors: Chiao-Shun Chuang, Tsung-Wei Pai, Yun-Pu Ku
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Patent number: 11335803Abstract: The structure of a field-effect transistor with a source-down configuration and process of making the transistor are described in this paper. The transistor is built in a semiconductor chip with a trench extending from top chip surface towards the bottom surface. The trench contains a conductive gate material embedded in a dielectric material in the trench. A conductive field plate is also embedded in the trench and extends from the top surface of the chip towards the bottom surface of the chip and splits the conductive gate electrode into two halves. The conductive field plate penetrates the trench and makes electrical contact with the heavily doped substrate near the bottom surface of the chip.Type: GrantFiled: July 27, 2020Date of Patent: May 17, 2022Inventors: Chiao-Shun Chuang, Che-Yung Lin
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Patent number: 11251152Abstract: A semiconductor device with reduced device resistance is disclosed. The semiconductor device comprises a semiconductor chip in which the chip thickness at the center portion of the chip where the circuit elements are disposed is uniform and is different from the chip thickness near the chip sides distant from the circuit elements.Type: GrantFiled: March 12, 2020Date of Patent: February 15, 2022Assignee: DIODES INCORPORATEDInventors: Duane Wilcoxen, Chiao-Shun Chuang, Rain Liu, Thomas Tsai, Will Zhang
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Publication number: 20210336618Abstract: An apparatus includes a capacitive device configured to provide bias power for a high-side switch, a gate drive path having variable resistance connected between the capacitive device and a gate of the high-side switch, wherein the gate drive path having variable resistance is of a first resistance value in response to a turn-on of the high-side switch, and the gate drive path having variable resistance is of a second resistance value in response to a turn-off of the high-side switch, and wherein the second resistance value is greater than the first resistance value, and a control switch connected between the gate of the high-side switch and ground.Type: ApplicationFiled: July 8, 2021Publication date: October 28, 2021Applicant: Diodes IncorporatedInventors: CHIAO-SHUN CHUANG, TA-CHUAN KUO, KE-HORNG CHEN
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Publication number: 20210288014Abstract: A semiconductor device with reduced device resistance is disclosed. The semiconductor device comprises a semiconductor chip in which the chip thickness at the center portion of the chip where the circuit elements are disposed is uniform and is different from the chip thickness near the chip sides distant from the circuit elements.Type: ApplicationFiled: March 12, 2020Publication date: September 16, 2021Applicant: Diodes IncorporatedInventors: Duane Wilcoxen, Chiao-Shun Chuang, Rain Liu, Thomas Tsai, Will Zhang
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Patent number: 11101796Abstract: An apparatus includes a capacitive device configured to provide bias power for a high-side switch, a gate drive path having variable resistance connected between the capacitive device and a gate of the high-side switch, wherein the gate drive path having variable resistance is of a first resistance value in response to a turn-on of the high-side switch, and the gate drive path having variable resistance is of a second resistance value in response to a turn-off of the high-side switch, and wherein the second resistance value is greater than the first resistance value, and a control switch connected between the gate of the high-side switch and ground.Type: GrantFiled: June 8, 2020Date of Patent: August 24, 2021Assignee: Diodes IncorporatedInventors: Chiao-Shun Chuang, TaChuan Kuo, Ke-Horng Chen
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Publication number: 20210211128Abstract: An apparatus includes a capacitive device configured to provide bias power for a high-side switch, a gate drive path having variable resistance connected between the capacitive device and a gate of the high-side switch, wherein the gate drive path having variable resistance is of a first resistance value in response to a turn-on of the high-side switch, and the gate drive path having variable resistance is of a second resistance value in response to a turn-off of the high-side switch, and wherein the second resistance value is greater than the first resistance value, and a control switch connected between the gate of the high-side switch and ground.Type: ApplicationFiled: June 8, 2020Publication date: July 8, 2021Applicant: Diodes IncorporatedInventors: Chiao-Shun Chuang, TaChuan Kuo, Ke-Horng Chen
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Publication number: 20210151596Abstract: The structure of a field-effect transistor with a source-down configuration and process of making the transistor are described in this paper. The transistor is built in a semiconductor chip with a trench extending from top chip surface towards the bottom surface. The trench contains a conductive gate material embedded in a dielectric material in the trench. A conductive field plate is also embedded in the trench and extends from the top surface of the chip towards the bottom surface of the chip and splits the conductive gate electrode into two halves. The conductive field plate penetrates the trench and makes electrical contact with the heavily doped substrate near the bottom surface of the chip.Type: ApplicationFiled: July 27, 2020Publication date: May 20, 2021Applicant: Diodes IncorporatedInventors: Chiao-Shun Chuang, Che-Yung Lin
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Patent number: 10170572Abstract: A power MOSFET or a power rectifier may be fabricated according to the invention to include a gate trench and a field plate trench. Both trenches can be formed with a two-step etching process as described in detail in the specification. The devices that embody this invention can be fabricated with higher packaging density and better and more tightly distributed device parameters such as the VF, RDSS, and BV.Type: GrantFiled: August 10, 2017Date of Patent: January 1, 2019Assignee: Diodes IncorporatedInventors: Yun-Pu Ku, Chiao-Shun Chuang, Cheng-Chin Huang
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Publication number: 20170345906Abstract: A power MOSFET or a power rectifier may be fabricated according to the invention to include a gate trench and a field plate trench. Both trenches can be formed with a two-step etching process as described in detail in the specification. The devices that embody this invention can be fabricated with higher packaging density and better and more tightly distributed device parameters such as the VF, RDSS, and BV.Type: ApplicationFiled: August 10, 2017Publication date: November 30, 2017Inventors: Yun-Pu Ku, Chiao-Shun Chuang, Cheng-Chin Huang
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Patent number: 9786753Abstract: A power MOSFET or a power rectifier may be fabricated according to the invention to include a gate trench and a field plate trench. Both trenches can be formed with a two-step etching process as described in detail in the specification. The devices that embody this invention can be fabricated with higher packaging density and better and more tightly distributed device parameters such as the VF, RDSS, and BV.Type: GrantFiled: July 13, 2015Date of Patent: October 10, 2017Assignee: Diodes IncorporatedInventors: Yun-Pu Ku, Chiao-Shun Chuang, Cheng-Chin Huang
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Publication number: 20170084703Abstract: A MOSFET device or a rectifier device with improved RDSON and BV performance has a repetitive pattern of field plate trenches disposed in a semiconductor chip. The semiconductor chip comprises a doped epi-layer, in which the dopant concentration progressively decreases from the top of the chip surface towards the bottom of the chip. The doped epi-layer may comprises strata of epi-layers of different dopant concentrations and the field plate trenches each terminate at a predetermined point in the strata.Type: ApplicationFiled: September 17, 2015Publication date: March 23, 2017Inventors: Yun-Pu Ku, Chiao-Shun Chuang, Cheng-Chin Huang
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Publication number: 20170018619Abstract: A power MOSFET or a power rectifier may be fabricated according to the invention to include a gate trench and a field plate trench. Both trenches can be formed with a two-step etching process as described in detail in the specification. The devices that embody this invention can be fabricated with higher packaging density and better and more tightly distributed device parameters such as the VF, RDSS, and BV.Type: ApplicationFiled: July 13, 2015Publication date: January 19, 2017Inventors: Yun-Pu Ku, Chiao-Shun Chuang, Cheng-Chin Huang
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Patent number: 8912621Abstract: During fabrication of a semiconductor device, a width of semiconductor mesas between isolation trenches in the semiconductor device is varied in different regions. In particular, the width of the mesas is smaller in a termination region of the semiconductor device than in a cell or active region. When an oxide layer is subsequently grown, the semiconductor mesas between the trenches in the termination region are at least partially consumed so that the semiconductor mesas in the cell region and the termination region have different heights. Therefore, a contact photomask is not needed to isolate the semiconductor mesas in the termination region. Furthermore, after a planarization operation (such as chemical mechanical polishing), the semiconductor device may have a planar top surface than if contact holes are created. This may allow the metal layer deposited on top of the cell region and the termination region to be flat.Type: GrantFiled: July 11, 2012Date of Patent: December 16, 2014Assignee: Diodes IncorporatedInventors: Chiao-Shun Chuang, Kai-Yu Chen, Cheng-Chin Huang
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Patent number: 8907325Abstract: A thin film transistor disposed on a substrate is provided. The thin film transistor includes a gate, a semi-conductive layer, a gate insulator, a source and a drain. The gate insulator is located between the gate and the semi-conductive layer. A light shows a specific color after passing through the gate insulator. The source and the drain are disposed on the semi-conductive layer. A pixel structure and a liquid crystal display panel having the pixel structure are also provided. The liquid crystal display panel can display colorful images without disposing a color filter array additionally so that the manufacturing process of the liquid crystal panel is simple and the manufacturing cost of the liquid crystal panel is low.Type: GrantFiled: October 26, 2007Date of Patent: December 9, 2014Assignee: Au Optronics CorporationInventors: Chiao-Shun Chuang, Fang-Chung Chen, Han-Ping David Shieh
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Patent number: 8766279Abstract: A SiC-based trench-type Schottky device is disclosed. The device includes: a SiC substrate having first and second surfaces; a first contact metal formed on the second surface and configured for forming an ohmic contact on the substrate; a drift layer formed on the first surface and including a cell region and a termination region enclosing the cell region; a plurality of first trenches with a first depth formed in the cell region; a plurality of second trenches with a second depth less than the first depth; a plurality of mesas formed in the substrate, each defined between neighboring ones of the trenches; an insulating layer formed on sidewalls and bottoms of the trenches; and a second contact metal formed on the mesas and the insulating layer, extending from the cell region to the termination region, and configured for forming a Schottky contact on the mesas of the substrate.Type: GrantFiled: December 26, 2012Date of Patent: July 1, 2014Assignee: Industrial Technology Research instituteInventors: Cheng-Tyng Yen, Young-Shying Chen, Chien-Chung Hung, Chwan-Ying Lee, Chiao-Shun Chuang, Kai-Yu Chen, Cheng-Chin Huang