Abstract: Provided herein may be a method for controlling program verify operations of a non-volatile memory and a corresponding circuit thereof. The method for controlling a program verify operation of a non-volatile memory, comprising: selecting a source line among source lines coupled to a plurality of planes respectively; measuring a voltage of the selected source line associated with target cells of the non-volatile memory to be verified in a first sensing operation; comparing the measured voltage of the selected source line with a reference voltage; and skipping the second sensing operation if the measured voltage of the selected source line is lower than the reference voltage.

Abstract: A page buffer circuit may include: a first node; a first switching circuit configured to pre-charge the bit-line based on a voltage provided to the first switching circuit; a sensing node; a second switching circuit configured to discharge the sensing node when the voltage value of the first node is lower than a voltage value associated with a voltage inputted to the second switching circuit during an evaluation period; a sense latch configured to latch a voltage being determined based on the voltage level of the sensing node, during a strobe period; and a third switching circuit configured to prevent the voltage value of the first node from being lower than a voltage value associated with a voltage inputted to the third switching circuit independently from the voltage at the sense latch.

Abstract: Provided herein may be a method for controlling program verify operations of a non-volatile memory and a corresponding circuit thereof. The method for controlling a program verify operation of a non-volatile memory, comprising: selecting a source line among source lines coupled to a plurality of planes respectively; measuring a voltage of the selected source line associated with target cells of the non-volatile memory to be verified in a first sensing operation; comparing the measured voltage of the selected source line with a reference voltage; and skipping the second sensing operation if the measured voltage of the selected source line is lower than the reference voltage.

Abstract: Disclosed herein is a NAND flash memory comprising a bit-line and a page buffer, the page buffer comprising: a first switching circuit arranged between a first node and the bit-line; a third switching circuit arranged between the first node and a sensing node and configured to discharge the sensing node during an evaluation period, a pre-charging period preceding the evaluation period; and a fourth switching circuit configured to provide a first pre-charging path to the bit-line through the first node and the first switching circuit from a first voltage source during the pre-charging period, wherein the sensing node is configured to be charged through a second pre-charging path during the pre-charging period, and the second pre-charging path is separated from the first pre-charging path by the third switching circuit during the pre-charging period.

Abstract: Disclosed herein is a NAND flash memory comprising a bit-line and a page buffer, the page buffer comprising: a first switching circuit arranged between a first node and the bit-line; a third switching circuit arranged between the first node and a sensing node and configured to discharge the sensing node during an evaluation period, a pre-charging period preceding the evaluation period; and a fourth switching circuit configured to provide a first pre-charging path to the bit-line through the first node and the first switching circuit from a first voltage source during the pre-charging period, wherein the sensing node is configured to be charged through a second pre-charging path during the pre-charging period, and the second pre-charging path is separated from the first pre-charging path by the third switching circuit during the pre-charging period.

Abstract: Disclosed herein is a flash memory including a bit-line and a page buffer circuit. The page buffer circuit may include: a first node; a first switching circuit configured to pre-charge the bit-line based on a voltage provided to the first switching circuit; a sensing node; a second switching circuit configured to discharge the sensing node when the voltage value of the first node is lower than a voltage value associated with a voltage inputted to the second switching circuit during an evaluation period; a sense latch configured to latch a voltage being determined based on the voltage level of the sensing node, during a strobe period; and a third switching circuit configured to prevent the voltage value of the first node from being lower than a voltage value associated with a voltage inputted to the third switching circuit independently from the voltage at the sense latch.

Abstract: A device for use with non-volatile memory, includes a first transistor of a first channel type coupled between first and second nodes, including a control gate supplied with a first control signal having a first phase, a second transistor of a second channel type different from the first channel type including a first terminal coupled to the first node, a second terminal coupled to a third node, a back gate coupled to the first terminal thereof, and a control gate supplied with a second control signal having a second phase substantially opposite to the first phase, a third transistor of the second channel type including a first terminal coupled to the second node, a second terminal coupled to the third node, a back gate coupled to the first terminal thereof, and a control gate supplied with the second control signal, and a protection circuit coupled between the first and second node.

Abstract: A device comprises a non-volatile memory array, a first selection circuit selecting whether to make a first connection path between a first bit line and a first circuit node, and selecting whether to make a second connection path between the first bit line and a second circuit node, a power supplying circuit supplying a power supply voltage to the first circuit node, the power supply voltage being, when the first connection path is selected to be made, supplied to the first bit line, and a first voltage supplying circuit supplying a first voltage to the second circuit node, the first voltage being, when the second connection path is selected to be made, supplied to the first bit line, the first voltage and the power supply voltage being higher than a ground potential, and the first voltage being higher than the power supply voltage.

Abstract: A device for use with non-volatile memory, includes a first transistor of a first channel type coupled between first and second nodes, including a control gate supplied with a first control signal having a first phase, a second transistor of a second channel type different from the first channel type including a first terminal coupled to the first node, a second terminal coupled to a third node, a back gate coupled to the first terminal thereof, and a control gate supplied with a second control signal having a second phase substantially opposite to the first phase, a third transistor of the second channel type including a first terminal coupled to the second node, a second terminal coupled to the third node, a back gate coupled to the first terminal thereof, and a control gate supplied with the second control signal, and a protection circuit coupled between the first and second node.

Abstract: A device comprises a non-volatile memory array, a first selection circuit selecting whether to make a first connection path between a first bit line and a first circuit node, and selecting whether to make a second connection path between the first bit line and a second circuit node, a power supplying circuit supplying a power supply voltage to the first circuit node, the power supply voltage being, when the first connection path is selected to be made, supplied to the first bit line, and a first voltage supplying circuit supplying a first voltage to the second circuit node, the first voltage being, when the second connection path is selected to be made, supplied to the first bit line, the first voltage and the power supply voltage being higher than a ground potential, and the first voltage being higher than the power supply voltage.

Abstract: A device includes a first transistor coupled between first and second nodes, and including a control gate supplied with a first control signal, a second transistor coupled between the first node and a third node, and including a control gate supplied with the first control signal, a third transistor coupled between the third node and a fourth node, and including a control gate supplied with a second control signal, a fourth transistor coupled between the fourth node and a fifth node, and including a control gate supplied with the second control signal, and a fifth transistor coupled between the fifth node and the second nodes, and including a control gate supplied with the first control signal. Each of the second and fifth transistors is smaller in threshold voltage than the first transistor.

Abstract: Disclosed herein is a device that includes an amplifier, a first transistor coupled between the first power supply line and the internal node and including a gate terminal supplied with a bias voltage, a second transistor coupled between the internal node and the second power supply line and including a gate terminal coupled to the output terminal of the amplifier, a third transistor coupled between the first power supply line and the output node and including a gate terminal coupled to the internal node, a divider configured to produce a first discharge path from the output node to the second power supply line to establish the feedback voltage to the amplifier, and a first switch circuit supplied with a first signal and coupled between the output node and the internal node.

Abstract: FLASH memory device contains at least one memory stack. The stack of transistors includes a first (or source) selector transistor, a second (or drain) selector transistor, and a plurality memory cell transistors connected in series therebetween. During an erase operation, each of the first and second selector transistors has a bias applied that releases the select transistors from an electrically floating state together with biasing each of the memory cell transistors.

Abstract: FLASH memory device contains at least one memory stack. The stack of transistors includes a first (or source) selector transistor, a second (or drain) selector transistor, and a plurality memory cell transistors connected in series therebetween. During an erase operation, each of the first and second selector transistors has a bias applied that releases the select transistors from an electrically floating state together with biasing each of the memory cell transistors.

Abstract: Devices and circuits for row driver in a memory device. The proposed row driver circuit architectures may reduce size of the row driver circuitry and enhance the row driver circuit's reliability. Specifically, the proposed embodiments of the row driver may reduce the required sizing of the boosting capacitor or alternatively eliminate the boosting capacitor entirely. Further, the embodiments of the row driver may reduce the risk of charge-leakage on K-nodes, enhancing the row driver's reliability in driving the x-path of the memory array.

Abstract: A device includes a first transistor coupled between first and second nodes, and including a control gate supplied with a first control signal, a second transistor coupled between the first node and a third node, and including a control gate supplied with the first control signal, a third transistor coupled between the third node and a fourth node, and including a control gate supplied with a second control signal, a fourth transistor coupled between the fourth node and a fifth node, and including a control gate supplied with the second control signal, and a fifth transistor coupled between the fifth node and the second nodes, and including a control gate supplied with the first control signal. Each of the second and fifth transistors is smaller in threshold voltage than the first transistor.

Abstract: Disclosed herein is a device that includes an amplifier, a first transistor coupled between the first power supply line and the internal node and including a gate terminal supplied with a bias voltage, a second transistor coupled between the internal node and the second power supply line and including a gate terminal coupled to the output terminal of the amplifier, a third transistor coupled between the first power supply line and the output node and including a gate terminal coupled to the internal node, a divider configured to produce a first discharge path from the output node to the second power supply line to establish the feedback voltage to the amplifier, and a first switch circuit supplied with a first signal and coupled between the output node and the internal node.

Abstract: Devices and circuits for voltage reference architectures that can increase the PSRR parameter by improving the saturation margin for an output transistor. For example, a device can include a current source coupled between a first power supply line and a circuit node, a voltage production circuit coupled between the circuit node and a second power supply line to produce a plurality of voltages respectively at voltage nodes thereof, a multiplexer coupled to the voltage nodes of the voltage production circuit and the output node and configured to select and output one of the voltages to the output node, and a control circuit configured to supply the one of the voltages to the circuit node.

Abstract: Disclosed herein is a device that includes at least one selection/non-selection voltage receiving line, at least one word line operatively coupled to the selection/non-selection voltage receiving line, and a plurality of memory cells coupled to the word line; a selection voltage source line; and a selection voltage supply circuit comprising a first switch circuit and a first driver circuit driving the first switch circuit to be turned ON or OFF, the first switch circuit including a first node coupled to the selection voltage source line, a second node coupled to the selection/non-selection voltage receiving line of the first memory plane and a third node coupled to the selection/non-selection voltage receiving line of the second memory plane, and the first driver circuit being provided in common to the first and second memory planes.

Abstract: Devices and circuits for voltage reference architectures that can increase the PSRR parameter by improving the saturation margin for an output transistor. For example, a device can include a current source coupled between a first power supply line and a circuit node, a voltage production circuit coupled between the circuit node and a second power supply line to produce a plurality of voltages respectively at voltage nodes thereof, a multiplexer coupled to the voltage nodes of the voltage production circuit and the output node and configured to select and output one of the voltages to the output node, and a control circuit configured to supply the one of the voltages to the circuit node.