Patents by Inventor Chiara Piglione

Chiara Piglione has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10122645
    Abstract: In one implementation, an input queue switch provides latency fairness across multiple input ports and multiple output ports. In one embodiment, each input port maintains a virtual output queue for each associate output port. The virtual output queues across multiple inputs are aggregated for each specific output port. The sum of the lengths of the virtual output queues is compared to a threshold, and based on the comparison, feedback may be generated to control the operation of the input port for subsequent packets. The feedback may instruct the input port to stop buffering or drop packets destined for the output port with the sum of the lengths of the virtual output queues associated to the specific output port that exceeds the threshold. In another embodiment, each packet has an arrival timestamp, and a virtual output queue having the oldest timestamp is selected first to dequeue.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: November 6, 2018
    Assignee: Cisco Technology, Inc.
    Inventors: Dipankar Bhatt Acharya, Guglielmo Morandin, Rong Pan, Chiara Piglione, Hiroshi Suzuki
  • Patent number: 9674104
    Abstract: An example method for adapting Proportional Integral controller Enhanced (PIE) algorithm for varying network conditions is provided and includes estimating an average dequeue rate at which packets are dequeued from a queue of packets maintained in a buffer in a network element operating, estimating a current queuing latency for the queue of packets based on the average dequeue rate, determining a target delay based on the average dequeue rate, the target delay varying with the average dequeue rate according to a predetermined relationship, and calculating a current drop probability associated with a probability that packets arriving at the buffer will be dropped or marked, the current drop probability being calculated using at least the current queuing latency and the target delay. In some embodiments, a threshold for a number of bytes dequeued from the buffer is estimated based on network conditions.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: June 6, 2017
    Assignee: CISCO TECHNOLOGY, INC
    Inventors: Rong Pan, Preethi Natarajan, Chiara Piglione, Mythili Suryanarayana Prabhu, Alon Bernstein, Frederick J. Baker
  • Patent number: 9246829
    Abstract: In one embodiment, a method includes estimating a current queuing latency, the estimated current queuing latency being associated with a queue of packets maintained in a buffer. The method also includes calculating a current drop or mark probability, the current drop or mark probability being associated with a probability that packets associated with the queue of packets will be dropped or marked. A rate at which the packets associated with the queue of packets are dequeued from the buffer is estimated in order to estimate the current queuing latency. The current drop or mark probability is calculated using the current estimated queuing latency.
    Type: Grant
    Filed: May 1, 2013
    Date of Patent: January 26, 2016
    Assignee: Cisco Technology, Inc.
    Inventors: Rong Pan, Preethi Natarajan, Chiara Piglione, Mythili Suryanarayana Prabhu, Frederick Juergens Baker, Bill Carroll VerSteeg, Vijaynarayanan Subramanian
  • Publication number: 20150131446
    Abstract: To reduce latency in a network device that buffer packets in different queues based on class of service, packets received from a network are stored in physical queues according to a class of service associated with the packets and a class of service associated with each of the physical queues. The physical queues are scheduled based quality of service requirements of their associated class of service. The physical queues are shadowed by virtual queues, and whether congestion exists in at least one of the virtual queues is determined. Packets departing from at least one of the physical queues are marked when congestion exists in at least one of the virtual queues. The service rate of the virtual queues is set to be less than or equal to a port link rate of the network device.
    Type: Application
    Filed: November 11, 2014
    Publication date: May 14, 2015
    Applicant: BROADCOM CORPORATION
    Inventors: Bruce Hui KWAN, Chiara Piglione, Puneet Agarwal, Vahid Tabatabaee
  • Publication number: 20140328175
    Abstract: In one embodiment, a method includes estimating a current queuing latency, the estimated current queuing latency being associated with a queue of packets maintained in a buffer. The method also includes calculating a current drop or mark probability, the current drop or mark probability being associated with a probability that packets associated with the queue of packets will be dropped or marked. A rate at which the packets associated with the queue of packets are dequeued from the buffer is estimated in order to estimate the current queuing latency. The current drop or mark probability is calculated using the current estimated queuing latency.
    Type: Application
    Filed: May 1, 2013
    Publication date: November 6, 2014
    Applicant: Cisco Technology, Inc.
    Inventors: Rong Pan, Preethi Natarajan, Chiara Piglione, Mythili Suryanarayana Prabhu, Frederick Juergens Baker, Bill Carroll VerSteeg, Vijaynarayanan Subramanian
  • Patent number: 8817807
    Abstract: An example method includes sending a virtual output queue (VOQ) length of a VOQ to an egress chip. The VOQ relates to a flow routed through an egress port associated with the egress chip. The method also includes receiving fair share information for the VOQ from the egress chip, and enforcing a control action on the incoming packets based on the fair share information. An ingress chip and the egress chip can be provided in a VOQ switch. The control action is a selected one of a group of actions, the group consisting of: (a) dropping packets, (b) pausing packets, and (c) marking packets. The method can further include receiving VOQ lengths of corresponding VOQs from respective ingress chips, where the VOQs relate to the flow. The method can also include calculating respective fair share information for each VOQ, and sending the fair share information to the respective ingress chips.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: August 26, 2014
    Assignee: Cisco Technology, Inc.
    Inventors: Hiroshi Suzuki, Rong Pan, Flavio Bonomi, Chien Fang, Chiara Piglione
  • Publication number: 20140161135
    Abstract: In one implementation, an input queue switch provides latency fairness across multiple input ports and multiple output ports. In one embodiment, each input port maintains a virtual output queue for each associate output port. The virtual output queues across multiple inputs are aggregated for each specific output port. The sum of the lengths of the virtual output queues is compared to a threshold, and based on the comparison, feedback may be generated to control the operation of the input port for subsequent packets. The feedback may instruct the input port to stop buffering or drop packets destined for the output port with the sum of the lengths of the virtual output queues associated to the specific output port that exceeds the threshold. In another embodiment, each packet has an arrival timestamp, and a virtual output queue having the oldest timestamp is selected first to dequeue.
    Type: Application
    Filed: December 7, 2012
    Publication date: June 12, 2014
    Applicant: Cisco Technology, Inc.
    Inventors: Dipankar Bhatt Acharya, Guglielmo Morandin, Rong Pan, Chiara Piglione, Hiroshi Suzuki
  • Publication number: 20130329577
    Abstract: An example method includes sending a virtual output queue (VOQ) length of a VOQ to an egress chip. The VOQ relates to a flow routed through an egress port associated with the egress chip. The method also includes receiving fair share information for the VOQ from the egress chip, and enforcing a control action on the incoming packets based on the fair share information. An ingress chip and the egress chip can be provided in a VOQ switch. The control action is a selected one of a group of actions, the group consisting of: (a) dropping packets, (b) pausing packets, and (c) marking packets. The method can further include receiving VOQ lengths of corresponding VOQs from respective ingress chips, where the VOQs relate to the flow. The method can also include calculating respective fair share information for each VOQ, and sending the fair share information to the respective ingress chips.
    Type: Application
    Filed: June 11, 2012
    Publication date: December 12, 2013
    Inventors: Hiroshi Suzuki, Rong Pan, Flavio Bonomi, Chien Fang, Chiara Piglione
  • Patent number: 8149710
    Abstract: In one embodiment, a method comprises the following steps: receiving a first set of inputs comprising a first plurality of entities and a first traffic behavior; determining a first region of a buffer corresponding to the first traffic behavior; assigning the first plurality of entities to the first region; determining hierarchical relationships between at least some of the first plurality of entities; determining a first shared buffer space of the first region; and assigning at least one threshold for each of the first plurality of entities. The threshold may comprise a maximum amount of the first shared buffer space that may be allocated to an entity. The method may also involve configuring a logic device to allocate the first shared buffer space dynamically according to the hierarchical relationships and the thresholds.
    Type: Grant
    Filed: July 5, 2007
    Date of Patent: April 3, 2012
    Assignee: Cisco Technology, Inc.
    Inventors: Davide Bergamasco, Valentina Alaria, Chiara Piglione, Michele Caramello
  • Patent number: 8005106
    Abstract: In one embodiment, apparatus and methods for apparatus and methods for fair bandwidth allocation are disclosed. In one embodiment, a method includes (i) determining a drop probability for each of a plurality of classes of packets being dropped or admitted to a queue, wherein each drop probability is based on a weighted fair bandwidth allocation process that is performed with respect to the plurality of classes and a plurality of packet arrival rates and predefined weights for such classes; and (ii) dropping a particular packet or admitting such particular packet to the queue based on the drop probability for such particular packet's class, wherein such dropping or admitting operation is further based on one or more drop precedence factors that are also determined periodically for each class if such one or more drop precedence factors are selected for such each class.
    Type: Grant
    Filed: May 21, 2009
    Date of Patent: August 23, 2011
    Assignee: Cisco Technology, Inc.
    Inventors: Rong Pan, Ming Zhang, Chiara Piglione, Valentina Alaria
  • Publication number: 20100296398
    Abstract: In one embodiment, apparatus and methods for apparatus and methods for fair bandwidth allocation are disclosed. In one embodiment, a method includes (i) determining a drop probability for each of a plurality of classes of packets being dropped or admitted to a queue, wherein each drop probability is based on a weighted fair bandwidth allocation process that is performed with respect to the plurality of classes and a plurality of packet arrival rates and predefined weights for such classes; and (ii) dropping a particular packet or admitting such particular packet to the queue based on the drop probability for such particular packet's class, wherein such dropping or admitting operation is further based on one or more drop precedence factors that are also determined periodically for each class if such one or more drop precedence factors are selected for such each class.
    Type: Application
    Filed: May 21, 2009
    Publication date: November 25, 2010
    Applicant: CISCO TECHNOLOGY, INC.
    Inventors: Rong Pan, Ming Zhang, Chiara Piglione, Valentina Alaria
  • Publication number: 20090010162
    Abstract: In one embodiment, a method comprises the following steps: receiving a first set of inputs comprising a first plurality of entities and a first traffic behavior; determining a first region of a buffer corresponding to the first traffic behavior; assigning the first plurality of entities to the first region; determining hierarchical relationships between at least some of the first plurality of entities; determining a first shared buffer space of the first region; and assigning at least one threshold for each of the first plurality of entities. The threshold may comprise a maximum amount of the first shared buffer space that may be allocated to an entity. The method may also involve configuring a logic device to allocate the first shared buffer space dynamically according to the hierarchical relationships and the thresholds.
    Type: Application
    Filed: July 5, 2007
    Publication date: January 8, 2009
    Applicant: Cisco Technology, Inc.
    Inventors: Davide Bergamasco, Valentina Alaria, Chiara Piglione, Michele Caramello