Abstract: One or more resistors or resistances are integrated in a 7-bit DVR or PVCOM integrated circuit. A 7-bit DVR or PVCOM integrated circuit includes a 7-bit DAC. The integrated resistors or resistances (R1, R2, or RSET, or any combination) reduces the number of external components, reduces the number of pins, and increases the accuracy of the DVR or PVCOM circuit. The least significant bit (LSB) of the DAC depends only on ratios of internal resistors, which can be made very accurate and independent of temperature.

Abstract: One or more resistors or resistances are integrated in a 7-bit DVR or PVCOM integrated circuit. A 7-bit DVR or PVCOM integrated circuit includes a 7-bit DAC. The integrated resistors or resistances (R1, R2, or RSET, or any combination) reduces the number of external components, reduces the number of pins, and increases the accuracy of the DVR or PVCOM circuit. The least significant bit (LSB) of the DAC depends only on ratios of internal resistors, which can be made very accurate and independent of temperature.

Abstract: One or more resistors or resistances are integrated in a 7-bit DVR or PVCOM integrated circuit. A 7-bit DVR or PVCOM integrated circuit includes a 7-bit DAC. The integrated resistors or resistances (R1, R2, or RSET, or any combination) reduces the number of external components, reduces the number of pins, and increases the accuracy of the DVR or PVCOM circuit. The least significant bit (LSB) of the DAC depends only on ratios of internal resistors, which can be made very accurate and independent of temperature.

Abstract: A method includes: detecting one of a short-to-ground condition and a short-to-supply condition at an output node; after a delay, selectively activating a feedback control transistor according to the detecting; detecting a first current passing through a first transistor using a second transistor sized to be smaller than the first transistor; mirroring the detected current using a plurality of transistors to form a feedback current; and providing the feedback current to a gate electrode of the first transistor according to the selectively activating the feedback control transistor.

Abstract: One or more resistors or resistances are integrated in a 7-bit DVR or PVCOM integrated circuit. A 7-bit DVR or PVCOM integrated circuit includes a 7-bit DAC. The integrated resistors or resistances (R1, R2, or RSET, or any combination) reduces the number of external components, reduces the number of pins, and increases the accuracy of the DVR or PVCOM circuit. The least significant bit (LSB) of the DAC depends only on ratios of internal resistors, which can be made very accurate and independent of temperature.

Abstract: In one embodiment, a method includes: detecting one of a short-to-ground condition and a short-to-supply condition at an output node; after a delay, selectively activating a feedback control transistor according to the detecting; detecting a first current passing through a first transistor using a second transistor sized to be smaller than the first transistor; mirroring the detected current using a plurality of transistors to form a feedback current; and providing the feedback current to a gate electrode of the first transistor according to the selectively activating the feedback control transistor.

Abstract: One or more resistors or resistances are integrated in a 7-bit DVR or PVCOM integrated circuit. 7-bit DVR or PVCOM integrated circuit includes a 7-bit DAC. The integrated resistors or resistances (R1, R2, or RSET, or any combination) reduces the number of external components, reduces the number of pins, increases the accuracy of the DVR or PVCOM circuit. The least significant bit (LSB) of the DAC depends only on ratios of internal resistors, which can be made very accurate and independent of temperature.

Abstract: In one embodiment, a method includes: detecting one of a short-to-ground condition and a short-to-supply condition at an output node; selectively activating a feedback control transistor according to the detecting; detecting a first current passing through a first transistor using a second transistor sized to be smaller than the first transistor; mirroring the detected current using a plurality of transistors to form a feedback current; and providing the feedback current to a gate electrode of the first transistor according to the selectively activating the feedback control transistor.

Abstract: In one embodiment, a method includes: detecting one of a short-to-ground condition and a short-to-supply condition at an output node; selectively activating a feedback control transistor according to the detecting; detecting a first current passing through a first transistor using a second transistor sized to be smaller than the first transistor; mirroring the detected current using a plurality of transistors to form a feedback current; and providing the feedback current to a gate electrode of the first transistor according to the selectively activating the feedback control transistor.

Abstract: In one aspect, apparatus and method are provided for communicating data in the form of transmission symbols conveyed in a carrier signal, wherein each transmission symbol is from a symbol set comprising a plurality of symbols which are collectively capable of representing any combination of values for at least three bits of data, wherein each symbol of the symbol set is defined with at most one transition of signal level in the carrier signal. In another aspect, apparatus and method are provided for communicating any combination of values for at least three data bits in the form of a respective transmission symbol conveyed in a carrier signal, wherein the transmission symbol is uniquely defined by a respective combination of a signal level transition, a lack of signal level transition, a signal region, and a cross-over between signal regions in the carrier signal.

Abstract: A synchronous bus system includes a clock line having a forward direction clock segment and a reverse direction clock segment connected to each of a plurality of devices. The forward direction clock segment carries a forward direction clock signal, and the reverse direction clock segment carries a reverse direction clock signal. Synchronization clock circuitry, provided in each device, receives the forward direction clock signal and the reverse direction clock signal. Using the received clock signals, the synchronization clock circuitry derives a universal synchronization clock signal which is synchronous throughout all devices. Skew correction circuitry, provided in at least a portion of the devices, corrects for skew between the universal synchronization clock signal and one or more data signals for transferring data between devices.

Abstract: An apparatus for providing multi-symbol signaling includes a multi-symbol encoder circuit. The multi-symbol encoder circuit is operable to encode data into a plurality of symbols, each symbol uniquely defined by a signal transition and a signal region in a carrier signal. A driver circuit, coupled to the multi-symbol encoder circuit, is operable to drive the carrier signal.

Abstract: A synchronous bus system includes a clock line having a forward direction clock segment and a reverse direction clock segment connected to each of a plurality of devices. The forward direction clock segment carries a forward direction clock signal, and the reverse direction clock segment carries a reverse direction clock signal. Synchronization clock circuitry, provided in each device, receives the forward direction clock signal and the reverse direction clock signal. Using the received clock signals, the synchronization clock circuitry derives a universal synchronization clock signal which is synchronous throughout all devices. Skew correction circuitry, provided in at least a portion of the devices, corrects for skew between the universal synchronization clock signal and one or more data signals for transferring data between devices.

Abstract: An I/O interface circuit includes an output buffer circuit and an input buffer circuit. The output buffer circuit can receive a first stream of data elements for output from the semiconductor chip, add a separate reference element for each data element in the first stream, and generate a first data transmission signal representing the data elements of the first stream and the respective reference elements. The input buffer circuit can receive a second data transmission signal representing data elements of a second stream and respective reference elements for the data elements of the second stream, sample the second data transmission signal to obtain voltage values for each data element of the second stream and the respective reference element, and interpret the voltage value for each data element of the second stream against the voltage value for the respective reference element in order to recover the data elements of the second stream.