Patents by Inventor Chidambaram G. Kallingal

Chidambaram G. Kallingal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150010851
    Abstract: One illustrative method disclosed herein includes the steps of decomposing an initial overall target exposure pattern into at least a first decomposed sub-target pattern and a second decomposed sub-target pattern, performing first and second retargeting processes on the first and second decomposed sub-target patterns while using the other sub-target pattern as a reference layer, respectively, to thereby define retargeted first and second decomposed sub-target patterns, respectively, and, after performing the first and second retargeting processes, performing at least one process operation to determine if each of the retargeted first decomposed sub-target pattern and the retargeted second decomposed sub-target pattern is in compliance with at least one design rule.
    Type: Application
    Filed: July 8, 2013
    Publication date: January 8, 2015
    Inventors: Chidambaram G. Kallingal, YuYang Sun
  • Patent number: 8921016
    Abstract: One illustrative method disclosed herein includes the steps of decomposing an initial overall target exposure pattern into at least a first decomposed sub-target pattern and a second decomposed sub-target pattern, performing first and second retargeting processes on the first and second decomposed sub-target patterns while using the other sub-target pattern as a reference layer, respectively, to thereby define retargeted first and second decomposed sub-target patterns, respectively, and, after performing the first and second retargeting processes, performing at least one process operation to determine if each of the retargeted first decomposed sub-target pattern and the retargeted second decomposed sub-target pattern is in compliance with at least one design rule.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: December 30, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Chidambaram G. Kallingal, YuYang Sun
  • Publication number: 20130232456
    Abstract: Disclosed herein are various OPC methods as it relates to the formation of masks to be used in multiple patterning processes, such as double patterning processes, and to the use of such masks during the manufacture of semiconductor devices. One illustrative method disclosed herein includes the steps of decomposing an initial overall target pattern into at least a first sub-target pattern and a second sub-target pattern, wherein each of the first and second sub-target patterns comprise at least one feature, and performing a first optical proximity correction process on the first sub-target pattern, wherein a position of at least one feature of the second sub-target pattern in the initial overall target pattern is considered when performing the first optical proximity correction process.
    Type: Application
    Filed: March 2, 2012
    Publication date: September 5, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Chidambaram G. Kallingal, Norman S. Chen, Jian Liu
  • Patent number: 6534378
    Abstract: The present invention advantageously provides a method for retaining a substantially transparent dielectric above alignment marks during polishing of the dielectric to ensure that the alignment marks are preserved for subsequent processing steps. According to an embodiment, alignment marks are etched into a semiconductor substrate. Thereafter, a pad oxide layer is deposited across the substrate surface, followed by the deposition of a first nitride layer. Isolation trenches which are deeper than the alignment mark trenches are formed spaced distances apart within the substrate. Optical lithography may be used to define the regions of the first nitride layer, the pad oxide layer, and the substrate to be etched. The isolation trenches thus become the only areas of the substrate not covered by the pad oxide layer and the first nitride layer. A substantially transparent dielectric, e.g., oxide, is then deposited across the semiconductor topography to a level spaced above the first nitride layer.
    Type: Grant
    Filed: August 31, 1998
    Date of Patent: March 18, 2003
    Assignee: Cypress Semiconductor Corp.
    Inventors: Krishnaswamy Ramkumar, Chidambaram G. Kallingal, Sriram Madhavan
  • Patent number: 6171180
    Abstract: The present invention advantageously provides a method for using an abrasive surface and a particle-free liquid to polish a dielectric, wherein the dielectric is deposited within an isolation trench and across a polish stop surface such that a recess region of the dielectric is spaced below the polish stop surface. In an embodiment, the dielectric is an isolation oxide, and the polish stop surface belongs to an upper surface of a nitride layer formed above a silicon-based substrate. The surface of the dielectric is positioned laterally adjacent the abrasive polishing surface such that the particle-free liquid is positioned at the interface between the dielectric and the polishing surface. The particle-free liquid is preferably deionized water, and the abrasive polishing surface is preferably a polymeric matrix entrained with particles composed of, e.g., ceria.
    Type: Grant
    Filed: March 31, 1998
    Date of Patent: January 9, 2001
    Assignee: Cypress Semiconductor Corporation
    Inventors: William W. C. Koutny, Jr., Chidambaram G. Kallingal, Krishnaswamy Ramkumar