Patents by Inventor Chie Sutou

Chie Sutou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7528449
    Abstract: A semiconductor device includes a plurality of gate electrodes, source and drain regions, a plurality of source contacts, a plurality of drain contacts, substrate contacts, and a salicide block. The gate electrodes are arrayed in parallel on a semiconductor region on a semiconductor substrate. The source and drain regions are formed in the semiconductor region on both sides of each gate electrode. The source contacts are formed on the source region. The drain contacts are formed on the drain region. The substrate contacts are formed on the semiconductor substrate and electrically connect to the semiconductor substrate. The salicide block is formed between the gate electrode and the plurality of drain contacts. The salicide block prevents silicidation on the drain region. The length of the salicide block in a channel length direction increases as the distance from the substrate contact increases.
    Type: Grant
    Filed: October 17, 2006
    Date of Patent: May 5, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Chie Sutou, Hirobumi Kawashima
  • Publication number: 20070090414
    Abstract: A semiconductor device includes a plurality of gate electrodes, source and drain regions, a plurality of source contacts, a plurality of drain contacts, substrate contacts, and a salicide block. The gate electrodes are arrayed in parallel on a semiconductor region on a semiconductor substrate. The source and drain regions are formed in the semiconductor region on both sides of each gate electrode. The source contacts are formed on the source region. The drain contacts are formed on the drain region. The substrate contacts are formed on the semiconductor substrate and electrically connect to the semiconductor substrate. The salicide block is formed between the gate electrode and the plurality of drain contacts. The salicide block prevents silicidation on the drain region. The length of the salicide block in a channel length direction increases as the distance from the substrate contact increases.
    Type: Application
    Filed: October 17, 2006
    Publication date: April 26, 2007
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Chie Sutou, Hirobumi Kawashima