Patents by Inventor Chieh-An CHANG

Chieh-An CHANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11935955
    Abstract: A device includes a fin extending from a substrate, a gate stack over and along sidewalls of the fin, a gate spacer along a sidewall of the gate stack, and an epitaxial source/drain region in the fin and adjacent the gate spacer. The epitaxial source/drain region includes a first epitaxial layer on the fin, the first epitaxial layer including silicon, germanium, and arsenic, and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including silicon and phosphorus, the first epitaxial layer separating the second epitaxial layer from the fin. The epitaxial source/drain region further includes a third epitaxial layer on the second epitaxial layer, the third epitaxial layer including silicon, germanium, and phosphorus.
    Type: Grant
    Filed: December 2, 2022
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yu Ma, Shahaji B. More, Yi-Min Huang, Shih-Chieh Chang
  • Publication number: 20240088182
    Abstract: In some embodiments, an image sensor is provided. The image sensor includes a photodetector disposed in a semiconductor substrate. A wave guide filter having a substantially planar upper surface is disposed over the photodetector. The wave guide filter includes a light filter disposed in a light filter grid structure. The light filter includes a first material that is translucent and has a first refractive index. The light filter grid structure includes a second material that is translucent and has a second refractive index less than the first refractive index.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Inventors: Cheng Yu Huang, Chun-Hao Chuang, Chien-Hsien Tseng, Kazuaki Hashimoto, Keng-Yu Chou, Wei-Chieh Chiang, Wen-Chien Yu, Ting-Cheng Chang, Wen-Hau Wu, Chih-Kung Chang
  • Publication number: 20240084040
    Abstract: The present invention provides antibody or the antigen-binding portion thereof bind to carbohydrate antigen, such as Globo series antigens (e.g. Globo H, SSEA-4 or SSEA-3). Also disclosed herein are pharmaceutical compositions and methods for the inhibition of cancer cells in a subject in need thereof. The pharmaceutical compositions comprise an antibody or an antigen-binding portion thereof and at least one pharmaceutically acceptable carrier.
    Type: Application
    Filed: February 9, 2022
    Publication date: March 14, 2024
    Inventors: Jiann-Shiun LAI, Hui-Wen CHANG, Yin-Chieh KUO, Chi-Sheng HSIA, Woan Eng CHAN, Ming-Tain LAI
  • Publication number: 20240085169
    Abstract: Imaging systems and techniques are described. An imaging system determines, based on image data of a scene received from an image sensor, a first plurality of pixel values corresponding to a first electromagnetic (EM) frequency domain and a second plurality of pixel values corresponding to a second EM frequency domain. The imaging system reduces the first plurality of pixel values using a plurality of cross-domain contamination values (based on the second plurality of pixel values) to generate a third plurality of pixel values. The imaging system determines a reconstructed pixel value based on a combination of at least an overexposed pixel value of the first plurality of pixel values and a corresponding pixel of the third plurality of pixel values. The imaging system outputs a reconstructed image that includes the reconstructed pixel value and a subset of the third plurality of pixel values.
    Type: Application
    Filed: September 14, 2022
    Publication date: March 14, 2024
    Inventors: Yun-Chieh CHANG, Jing WANG, Xiaoyun JIANG
  • Publication number: 20240088267
    Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yi PENG, Chih Chieh YEH, Chih-Sheng CHANG, Hung-Li CHIANG, Hung-Ming CHEN, Yee-Chia YEO
  • Publication number: 20240087951
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first metal layer over a substrate, forming a dielectric layer over the first metal layer. The method includes forming a trench in the dielectric layer, and performing a surface treatment process on a sidewall surface of the trench to form a hydrophobic layer. The hydrophobic layer is formed on a sidewall surface of the dielectric layer. The method further includes depositing a metal material in the trench and over the hydrophobic layer to form a via structure.
    Type: Application
    Filed: November 17, 2023
    Publication date: March 14, 2024
    Inventors: Chun-Hao Kung, Chih-Chieh Chang, Kao-Feng Liao, Hui-Chi Huang, Kei-Wei Chen
  • Patent number: 11926266
    Abstract: An installing module includes a seat bracket, a plurality of lower gaskets, a device bracket and an upper gasket. The seat bracket includes a first locking plate and a second locking plate locked to each other. The first locking plate includes a first concave and the second locking plate includes a second concave corresponding to the first concave. The lower gaskets are respectively disposed on the first concave and the second concave. The lower gaskets face each other and jointly define a lower assembly hole and are disposed on a lower side of a head-support fixer of a car seat. The device bracket is locked to the seat bracket and an electronic device is pivotally coupled to the device bracket. The upper gasket is disposed between the device bracket and the head-support fixer, and the head-support fixer is clamped between the upper gasket and the lower gaskets.
    Type: Grant
    Filed: August 26, 2022
    Date of Patent: March 12, 2024
    Assignee: PEGATRON CORPORATION
    Inventors: Shih-Wei Yeh, Chien-Chih Lin, Yi-Ming Chou, Chun-Chieh Chang
  • Patent number: 11929767
    Abstract: A transmission interface between at least a first module and a second module is proposed. The transmission interface includes at least two physical transmission mediums. Each physical transmission medium is arranged to carry a multiplexed signal in which at least two signals are integrated. The at least two physical transmission mediums include a first physical transmission medium arranged to carry a first multiplexed signal including a first IF signal and a reference clock signal. The first IF signal and the reference clock signal are at different frequencies.
    Type: Grant
    Filed: August 16, 2022
    Date of Patent: March 12, 2024
    Assignee: MEDIATEK INC.
    Inventors: Chieh-Hsun Hsiao, Ming-Chou Wu, Wen-Chang Lee, Narayanan Baskaran, Wei-Hsin Tseng, Jenwei Ko, Po-Sen Tseng, Hsin-Hung Chen, Chih-Yuan Lin, Caiyi Wang
  • Patent number: 11927799
    Abstract: A data transmission system is disclosed. The data transmission system includes at least one signal processing device, at least one conversion device, at least one antenna device, and at least one flexible printed circuit board. The at least one signal processing device is configured to generate or receive at least one data. The at least one conversion device is configured to transform between the at least one data and an optical signal. The at least one antenna device is configured to obtain the at least one data according to the optical signal, and configured to receive or transmit the at least one data wirelessly. The at least one flexible printed circuit board includes at least one conductive layer and at least one optical waveguide layer. The at least one optical waveguide layer is configured to transmit the optical signal.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: March 12, 2024
    Inventors: Po-Kuan Shen, Chun-Chiang Yen, Chiu-Lin Yu, Kai-Lun Han, Jenq-Yang Chang, Mao-Jen Wu, Chao-Chieh Hsu
  • Publication number: 20240079075
    Abstract: A memory test circuit is provided. The memory test circuit is disposed in a memory chip and electrically coupled to a memory macro of the memory chip. A high speed clock receives an input signal and an external clock signal. The input signal includes a plurality of test bits. A finite state machine controller provides a pattern type. A pattern generator generates and provides a test signal to at least one memory cell of the memory chip to write the test signal to the at least one memory cell based on the pattern type and the external clock signal. A test frequency of the test signal is determined based on the high speed clock. An output comparator outputs a comparison signal based on a difference between the test signal and a readout signal corresponding to the test signal read from the at least one memory cell.
    Type: Application
    Filed: January 12, 2023
    Publication date: March 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui-Jen Wu, Jen-Chieh Liu, Yi-Lun Lu, Win-San Khwa, Meng-Fan Chang
  • Publication number: 20240079887
    Abstract: The present invention provides a protection circuit applied to a battery module, which includes a self-control protector, a switch element and a voltage clamping loop; the self-control protector includes a fuse unit and a heater; when the switch element receives a control signal, the switch element will be turned on; when the switch element is turned on, the voltage clamping loop provides a clamp voltage to clamp a working current passing through the self-control protector within a current range where the fuse unit can be blown; and as such, the fuse unit of the self-control protector will be blown by the working current heating the heater.
    Type: Application
    Filed: July 10, 2023
    Publication date: March 7, 2024
    Inventors: Wen-Fan Chang, Chun-Chieh Li, Jung-Nan Chien
  • Publication number: 20240079080
    Abstract: A memory test circuit is provided. The memory test circuit is disposed in a memory array and including: a test array, including test cells out of memory cells of the memory array; a write multiplexer, configured to selectively output one of a test signal and a reference voltage based on a write measurement signal, wherein the test signal is output to write into at least one test cell and the reference voltage is output to a sense amplifier; and a read multiplexer, configured to selectively receive and output one of a readout signal corresponding to the test signal and an amplified signal based on a read measurement signal, wherein the readout signal is read from the at least one test cell and the amplified signal is obtained for a read margin evaluation from the sense amplifier by amplifying a voltage difference between the readout signal and the reference voltage.
    Type: Application
    Filed: September 1, 2022
    Publication date: March 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui-Jen Wu, Jen-Chieh Liu, Yi-Lun Lu, Win-San Khwa, Meng-Fan Chang
  • Patent number: 11923252
    Abstract: A semiconductor device includes a first set of nanostructures stacked over a substrate in a vertical direction, and each of the first set of nanostructures includes a first end portion and a second end portion, and a first middle portion laterally between the first end portion and the second end portion. The first end portion and the second end portion are thicker than the first middle portion. The semiconductor device also includes a first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures, and a gate structure around the first plurality of semiconductor capping layers.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sai-Hooi Yeong, Bo-Feng Young, Chi-On Chui, Chih-Chieh Yeh, Cheng-Hsien Wu, Chih-Sheng Chang, Tzu-Chiang Chen, I-Sheng Chen
  • Patent number: 11921434
    Abstract: An apparatus includes a vacuum chamber, a reflective optical element arranged in the vacuum chamber and configured to reflect an extreme ultra-violet (EUV) light, and a cleaning module positioned in the vacuum chamber. the cleaning module is operable to provide a mitigation gas flowing towards the reflective optical element and provide a hydrogen-containing gas flowing towards the reflective optical element. The mitigation gas mitigates, by chemical reaction, contamination of the reflective optical element.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Hao Chang, Norman Chen, Jeng-Horng Chen, Kuo-Chang Kau, Ming-Chin Chien, Shang-Chieh Chien, Anthony Yen, Kevin Huang
  • Patent number: 11923386
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a first photodetector disposed in a first pixel region of a semiconductor substrate and a second photodetector disposed in a second pixel region of the semiconductor substrate. The second photodetector is laterally separated from the first photodetector. A first diffuser is disposed along a back-side of the semiconductor substrate and over the first photodetector. A second diffuser is disposed along the back-side of the semiconductor substrate and over the second photodetector. A first midline of the first pixel region and a second midline of the second pixel region are both disposed laterally between the first diffuser and the second diffuser.
    Type: Grant
    Filed: April 24, 2023
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Keng-Yu Chou, Chun-Hao Chuang, Kazuaki Hashimoto, Wei-Chieh Chiang, Cheng Yu Huang, Wen-Hau Wu, Chih-Kung Chang
  • Patent number: D1017061
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: March 5, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chih-Hsien Wang, Shih-Chieh Chang, Yan-Jun Wang, Peng-Hui Wang, Ming-Chieh Cheng
  • Patent number: D1017062
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: March 5, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chih-Hsien Wang, Shih-Chieh Chang, Chuan-Hsi Chang, Peng-Hui Wang, Ming-Chieh Cheng
  • Patent number: D1018441
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: March 19, 2024
    Assignee: Cheng Shin Rubber Industrial Co., Ltd.
    Inventors: Yu Chieh Chen, Yu Shiuan Lin, Chia Hao Chang, Ku Wei Liao, Yi Ru Chen
  • Patent number: D1018526
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: March 19, 2024
    Assignee: Dell Products L.P.
    Inventors: Wei-Yi Li, Chih-Chieh Chang
  • Patent number: D1018891
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: March 19, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chih-Hsien Wang, Shih-Chieh Chang, Peng-Hui Wang, Ming-Chieh Cheng, Xiu-Yi Lin