Abstract: A semiconductor device includes a first set of nanostructures stacked over a substrate in a vertical direction, and each of the first set of nanostructures includes a first end portion and a second end portion, and a first middle portion laterally between the first end portion and the second end portion. The first end portion and the second end portion are thicker than the first middle portion. The semiconductor device also includes a first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures, and a gate structure around the first plurality of semiconductor capping layers.

Abstract: A lighting device includes a driver, a first light string, a second light string, a constant current controller and a pulse width modulation controller. The driver is configured to provide a DC driving current to a shunt node. The first light string is electrically coupled between the shunt node and a ground terminal, and the first light string is driven by a first pulsating direct current. The second light string and the constant current controller are electrically coupled in series between the shunt node and the ground terminal. The pulse width modulation controller is configured to provide a pulse signal to the constant current controller, and the constant current controller controls a pulse frequency of a second pulsating direct current supplied for the second light string according to the pulse signal.

Abstract: The purpose of the present invention is to provide a method for calculating a VC dimension boundary in a quantum circuit, the method comprising: a step in which a computer acquires the depth L of the quantum circuit; a step in which the computer acquires the width n of the quantum circuit; and a step in which the computer identifies the VC dimension boundary in the quantum circuit on the basis of the depth L and the width n.

Abstract: A manufacturing method of an aluminum battery includes: providing an aluminum electrode sheet having an oxide layer; soaking the aluminum electrode sheet in a first ionic liquid in a nitrogen atmosphere to remove the oxide layer, such that the aluminum electrode sheet has an exposed part of aluminum metal; removing the aluminum electrode sheet from the first ionic liquid and used as a negative electrode of the aluminum battery; and providing electrolyte. The exposed part of aluminum metal is in direct contact with the electrolyte.

Abstract: A surgical instrument includes a rod and a push portion. The push portion includes a first end connected to an end of the rod and a second end having a blade portion. The push portion includes a plurality of grooves. The plurality of grooves is recessed in a surface of the push portion and is spaced from each other. Each two adjacent grooves has a rib formed therebetween. A top face of a cross section of each rib is the surface of the push portion. Each rib has a guiding face on the cross section of the push portion. The guiding face is connected to the surface of the push portion. The guiding face faces a rotating direction of the rod. An angle between the guiding face and the surface of the push portion in the cross section is greater than 90°.

Abstract: A removal method applied to an aluminum electrode sheet with an oxide layer, including a soaking step. The soaking step includes soaking the aluminum electrode sheet in an ionic liquid to remove the oxide layer, such that the aluminum electrode sheet has an exposed part of aluminum metal, and the soaking step is performed in a nitrogen atmosphere.

Abstract: A method for fabricating a memory device includes: providing a substrate; forming a first dielectric layer over the substrate; forming a plurality of conductive layers and a plurality of dielectric layers alternately and horizontally disposed on the substrate; forming a channel column structure on the substrate and in the plurality of conductive layers and the plurality of dielectric layers, where a side wall of the channel column structure is in contact with the plurality of conductive layers; forming a second dielectric layer covering the first dielectric layer; and forming, in the first and second dielectric layers, a conductive column structure adjacent to the channel column structure and in contact with one of the plurality of conductive layers, where the conductive column structure includes a liner insulating layer as a shell layer.

Abstract: An image sensor device is provided. The image sensor device includes a semiconductor substrate having a front surface, a back surface opposite to the front surface, and a light-sensing region close to the front surface. The image sensor device includes an insulating layer covering the back surface and extending into the semiconductor substrate. The protection layer has a first refractive index, and the first refractive index is less than a second refractive index of the semiconductor substrate and greater than a third refractive index of the insulating layer, and the protection layer conformally and continuously covers the back surface and extends into the semiconductor substrate. The image sensor device includes a reflective structure surrounded by insulating layer in the semiconductor substrate.

Abstract: A fixed focus lens includes a first lens group with a negative refractive power, an aperture stop, and a second lens group with a positive refractive power arranged in order from a first side to a second side. The first lens group has at least two lenses including at least one aspheric lens. The second lens group includes at least five lenses, the at least five lenses comprising a first compound lens and a second compound lens. A difference between a maximum Abbe number and a minimum Abbe number for all lenses of the first compound lens is greater than 50, and a difference between a maximum Abbe number and a minimum Abbe number for all lenses of the second compound lens is greater than 45.

Abstract: An optical imaging system includes five lens elements, the five lens elements being, in order from an object side to an image side: a first lens element having positive refractive power; a second lens element having negative refractive power; a third lens element having positive refractive power; a fourth lens element having positive refractive power; and a fifth lens element having negative refractive power.

Abstract: The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.

Abstract: The present disclosure proposes a service plan automatic generation system and operation method thereof. The operation method includes a method for generating standardized items based on a service record, which includes the following steps: analyzing multiple instances to generate multiple feature tags, generating multiple word frequency vectors corresponding to the feature tags according to the instances, and performing an aggregation procedure for a plurality of times. Each time performing the aggregation procedure includes: executing a clustering algorithm to divide multiple instances into multiple groups, analyzing multiple variable parts and an identical part of multiple feature vectors in each group, outputting the variable parts as feature tag sets, and using the identical part as an index of the group, when a stop condition is detected, the index generated by the aggregation procedure in the last time is outputted as a standardized item.

Abstract: The present disclosure provides a calibration method and readable computer storage medium. The calibration method includes: configuring a reference signal source to output a reference signal; delaying the reference signal through a delay chain to output a delay signal; synchronous sampling the reference signal and the delay signal; adding 1 count and obtaining a final count value when the sampling result is in the preset state; determining whether a ratio between the count value and the first quantity is within a preset range; obtaining the average delay time according to the time width of the reference signal wave and the number of the delay units opened in the delay chain when the ratio is within the preset range; and outputting a control signal to the clock recovery circuit according to the average delay time to calibrate the delay time of the clock recovery circuit.

Abstract: A power control system of a rack heat-dissipation system, which receives output voltages of a rack power supply and a module power supply, includes a first control module and a second control module operating in parallel. The first control module includes a first switching unit, a first voltage converting unit and a first monitoring unit. The second control module includes a second switching unit, a second voltage converting unit and a second monitoring unit. The first monitoring unit is connected to the rack power supply, the module power supply, the first switching unit and the first voltage converting unit, and the second monitoring unit is connected to the rack power supply, the module power supply, the second switching unit and the second voltage converting unit. The heat dissipation system can be kept in the normal operation even if one of the control modules is failed.

Abstract: A timing controller and a polarity control method thereof are provided. The timing controller includes a line buffer and a check circuit. The line buffer temporarily stores a plurality of sub-pixel data of a current sub-pixel row in an image frame so as to transmit the plurality of sub-pixel data of the current sub-pixel row to a source driver. The check circuit generates a polarity command corresponding to the current sub-pixel row for the source driver to set a polarity inversion mode of the current sub-pixel row. The check circuit checks the plurality of sub-pixel data of the current sub-pixel row so as to determine whether to dynamically change the polarity inversion mode of the current sub-pixel row.

Abstract: A ceramic substrate structure includes a ceramic board, a first conductive layer, a second conductive layer and a heat dissipation layer. The ceramic board has a first surface and a second surface opposite to each other. Each of the first surface and the second surface is a single surface extending continuously. The first conductive layer is mounted on the first surface of the ceramic board. The second conductive layer is mounted on the first surface of the ceramic board. The second conductive layer is adjacent to the first conductive layer and have different thicknesses. The heat dissipation layer is mounted on the second surface of the ceramic board. The heat dissipation layer includes a first heat dissipation portion corresponding to the first conductive layer and a second heat dissipation portion corresponding to the second conductive layer, and the second heat dissipation portion has a patterned region.

Abstract: A manufacturing method of a semiconductor structure including following steps is provided. A first sacrificial layer and a second sacrificial layer are formed in a first substrate. A first device layer including a first dielectric structure and a first landing pad is formed on the first substrate. A second device layer including a second dielectric structure and a second landing pad is formed on a second substrate. The first dielectric structure is bonded to the second dielectric structure. A portion of the first substrate is removed to expose the first sacrificial layer and the second sacrificial layer. An etch-back process is performed by using the first substrate as a mask to form a first opening exposing the first landing pad and a second opening exposing the second landing pad. A first TSV structure and a second TSV structure are respectively formed in the first opening and the second opening.

Abstract: Aspects of the disclosure provide a frame processor for processing frames with aliasing artifacts. For example, the frame processor can include a super-resolution (SR) and anti-aliasing (AA) engine and an attention reference frame generator coupled to the SR and AA engine. The SR and AA engine can be configured to enhance resolution and remove aliasing artifacts of a frame to generate a first high-resolution frame with aliasing artifacts and a second high-resolution frame with aliasing artifacts removed. The attention reference frame generator can be configured to generate an attention reference frame based on the first high-resolution frame and the second high-resolution frame.