Abstract: A fast division method which uses a smaller quotient digit set of {?1, 1} than {?1, 0, 1} that is used by known algorithms, therefore accelerates the speed of calculation. Partial remainders can be computed with the signals of remainders decided independently and in parallel. By taking the absolute values of the remainders, we can successively subtract the remainders without the need of knowing the signs of remainders, while signs of the remainders can be decided in parallel and independently at the same time. The algorithm adopts non-restoring division operation and CSA type of operation for fast subtraction. The algorithm is also an on-line algorithm that facilitates highly pipelined operation while it is much simpler than the existing on-line algorithms.

Abstract: A track-number seeking algorithm and a seeking means for the dynamic modification of the computation of track numbers in an optical storage device employs a down counter, an up counter and a microprocessor. First, a rotation number of an optical storage disk in the microprocessor, a track error zero crossing signal of the down counter and the up counter are reset, a static track seeking number of the down counter is set, and a seeking operation is performed. The seeking operation reads the rotation number and the track error zero crossing signal, computes a residual track number, and judges whether an overflow flag is to be sent. If the overflow flag is sent, then, the rotation number is added, a pulse number of a feedback signal is reset, and the next step is to judge whether the seeking operation is outward or not. If the overflow flag is not sent, the next step is to judge directly whether the seeking operation is outward or not.

Abstract: A fast square root method which separates the sign detection operation of the remainder from the remainder subtraction operation. By taking the absolute values of the remainders, the method can successively subtract the remainder without knowing the signs of remainders, while signs of the remainder can be detected in parallel fashion and independently. The method also uses a smaller square root digit set of {-1, 1} than {-1, 0, 1} that is used by many known fast algorithms. This digit set facilitates fast conversion of the results to binary representations. Together with some hardware design techniques, the square root method can be realized and pipelined in simple circuits.

Abstract: A fast divider is disclosed in the present invention. It utilizes a division method which uses a smaller quotient digit set of {-1, 1} than {-1, 0, 1} that used by known algorithms, therefore accelerates the speed of calculation. Partial remainders are computed with the signs of remainders decided independently and in parallel. By taking the absolute values of the remainders, the remainders are successively subtracted without the need of knowing the signs of remainders, while signs of the remainders can be decided in parallel and independently at the same time. The method adopts non-restoring division operation and CSA (carry save adder) type of operation for fast subtraction. The method is also an on-line algorithm that facilitates highly pipelined operations while it is much simpler than the existing on-line algorithms.