Patents by Inventor Chieh-Hung Chen

Chieh-Hung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240157063
    Abstract: A drug delivery device including a main housing and a drug delivery module is provided. The main housing has an internal space. The drug delivery module is disposed in the internal space so as to be isolated from an external environment. The drug delivery module includes a drug bottle that contains a liquid drug and a driver that is connected to the drug bottle. The driver is configured to push the liquid drug to pass through a drug nebulization structure of the drug bottle such that the liquid drug is nebulized into a nebulized drug.
    Type: Application
    Filed: November 14, 2023
    Publication date: May 16, 2024
    Inventors: Chieh-Sheng Cheng, JUI-SHUI CHEN, YI-HUNG WANG
  • Publication number: 20240107087
    Abstract: The subject application relates to a server, terminal and non-transitory computer-readable medium. The server for handling streaming data for a live streaming, comprising one or a plurality of processors, wherein the one or plurality of processors execute a machine-readable instruction to perform: recording the streaming data for the live streaming; storing the streaming data as archive contents with first identifier; receiving interaction information during the live streaming; storing the interaction information as contexts with second identifier, transmitting the archive contents with first identifier to a first user terminal; and transmitting the contexts to the first user terminal according to the first identifier and the second identifier. According to the subject application, the archive contents may be more immersive and the user experience may be enhanced.
    Type: Application
    Filed: June 26, 2023
    Publication date: March 28, 2024
    Inventors: Yu-Chuan CHANG, Kun-Ze LI, Che-Wei LIU, Chieh-Min CHEN, Kuan-Hung LIU
  • Patent number: 11929767
    Abstract: A transmission interface between at least a first module and a second module is proposed. The transmission interface includes at least two physical transmission mediums. Each physical transmission medium is arranged to carry a multiplexed signal in which at least two signals are integrated. The at least two physical transmission mediums include a first physical transmission medium arranged to carry a first multiplexed signal including a first IF signal and a reference clock signal. The first IF signal and the reference clock signal are at different frequencies.
    Type: Grant
    Filed: August 16, 2022
    Date of Patent: March 12, 2024
    Assignee: MEDIATEK INC.
    Inventors: Chieh-Hsun Hsiao, Ming-Chou Wu, Wen-Chang Lee, Narayanan Baskaran, Wei-Hsin Tseng, Jenwei Ko, Po-Sen Tseng, Hsin-Hung Chen, Chih-Yuan Lin, Caiyi Wang
  • Publication number: 20190090367
    Abstract: An electronic device casing includes a main casing and a flexible member. The main casing includes a first surface and a second surface opposite to each other, an opening passing through the first surface and the second surface, and a fixing member located near the opening and protruding from the second surface. The flexible member and the main casing are integrally formed by double injection molding. The flexible member is disposed on the second surface and covers the opening. The fixing member passes through the flexible member. A manufacturing method of electronic device casing is further provided.
    Type: Application
    Filed: November 9, 2017
    Publication date: March 21, 2019
    Applicant: Lite-On Technology Corporation
    Inventors: Jun-Wen Teng, Chieh-Hung Chen
  • Patent number: 8559653
    Abstract: A multi-channel decoding method includes: receiving an input signal to generate a channel output signal; providing a first test signal serving as the input signal in a first calibration mode; and adjusting a DC voltage level of the channel output signal with a first calibration signal by reducing a difference between a first predetermined reference signal level and a DC voltage level of the channel output signal generated from the first test signal.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: October 15, 2013
    Assignee: Mediatek Inc.
    Inventors: Chieh-Hung Chen, Tsung-Ling Li, Chia-Huang Fu
  • Patent number: 8331890
    Abstract: A FM receiver comprises an IF filter, a demodulator and a decoder. The IF filter generates an RSSI and a FM modulated signal in response to a FM signal. The demodulator comprises a duty-to-voltage amplifier for amplifying a peak of a MPX signal. The duty-to-voltage amplifier comprises a current source, a switch and a current splitter. The current source generates a current. The switch controls a flow of the first current in response to a PWM signal. The current splitter splits the flow of the current into a sub-flow in response to the RSSI. The peak of the MPX signal is proportional to the sub-flow. The decoder receives the MPX signal to generate an audio signal to play sound.
    Type: Grant
    Filed: February 17, 2009
    Date of Patent: December 11, 2012
    Assignee: MediaTek Inc.
    Inventors: Hsiang-Hui Chang, Chieh Hung Chen
  • Publication number: 20120076309
    Abstract: A multi-channel decoding method includes: receiving an input signal to generate a channel output signal; providing a first test signal serving as the input signal in a first calibration mode; and adjusting a DC voltage level of the channel output signal with a first calibration signal by reducing a difference between a first predetermined reference signal level and a DC voltage level of the channel output signal generated from the first test signal.
    Type: Application
    Filed: December 1, 2011
    Publication date: March 29, 2012
    Inventors: Chieh-Hung Chen, Tsung-Ling Li, Chia-Huang Fu
  • Patent number: 8144878
    Abstract: An FM receiver and a pilot detector thereof, and a method for determining a type of a processed signal are provided. The FM receiver comprises a demodulator, a band pass filter (BPF), and a pilot detector. The demodulator generates a multiplexed (MPX) signal. The BPF filters the MPX signal to generate a pilot signal. The pilot detector comprises a signal addition device and a comparator. The signal addition device adds the processed signal for a period of time and to generate a result signal in response to the addition. The comparator compares the result signal with a reference to determine whether the type is stereo. The method comprises the steps of: adding the processed signal for a period of time; generating a result signal in response to the addition; and comparing the result signal with a reference to determine whether the type is stereo.
    Type: Grant
    Filed: March 6, 2006
    Date of Patent: March 27, 2012
    Assignee: MediaTek Inc.
    Inventor: Chieh Hung Chen
  • Patent number: 8094836
    Abstract: A multi-channel decoding method includes: receiving an input signal to generate a first channel output signal and a second channel output signal, wherein the input signal is mixed with a specific clock signal; and gradually changing an amplitude of the specific clock signal from a first value to a second value when switching from a first mode corresponding to a first number of channels to a second mode corresponding to a second number of channels. Systems utilizing the method and another method further comprising calibration are also disclosed.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: January 10, 2012
    Assignee: Mediatek Inc.
    Inventors: Chieh-Hung Chen, Tsung-Ling Li, Chia-Huang Fu
  • Patent number: 8045717
    Abstract: A stereo decoder and a method therefor are provided. The stereo decoder receives a MPX signal from an FM demodulator, and comprises a first auto-calibration circuit, a band-pass filter, a second auto-calibration circuit, a slicer and a PLL circuit. The first auto-calibration circuit generates a first control signal. The band-pass filter generates the pilot signal by filtering the MPX signal with a center frequency set by the first control signal. The second auto-calibration circuit generates a second control signal. The slicer converts the pilot signal into a square wave signal. The PLL circuit comprises a voltage controlled oscillator for generating an oscillation frequency in response to the second control signal. The PLL circuit receives the square wave signal to generate the reference signal around the predetermined frequency in response to the oscillation frequency.
    Type: Grant
    Filed: April 13, 2006
    Date of Patent: October 25, 2011
    Assignee: Media Tek Inc.
    Inventors: Chieh Hung Chen, Hsiang-Hui Chang, Chih-Chien Huang
  • Patent number: 7957698
    Abstract: A calibration circuit for calibrating an output level of a demodulator includes a test signal generator, an RSSI module and a calibration module. The test signal generator generates a test signal, and the RSSI module detects the test signal to generate a control signal, wherein the control signal controls the demodulator to process the test signal to generate a determined output signal. The calibration module then calibrates the RSSI module according to the output signal in order to calibrate the output level of the demodulator. When the control signal is utilized to selectively enable or disable a soft-mute function of the demodulator, the calibration module can be utilized to calibrate or determine the soft-mute function of the demodulator.
    Type: Grant
    Filed: March 11, 2008
    Date of Patent: June 7, 2011
    Assignee: Mediatek Inc.
    Inventors: Tsung-Ling Li, Hsiang-Hui Chang, Chia-Huang Fu, En-Hsiang Yeh, Hsueh-Kun Liao, Chieh-Hung Chen
  • Patent number: 7822211
    Abstract: A stereo decoding system comprises an oscillator, a bandpass filter, a PLL unit and a stereo decoder. The oscillator generates a first signal with a center frequency. The bandpass filter receives a stereo multiplexed signal and the first signal to filter out a pilot signal. The PLL unit receives the pilot signal to generate a PLL output signal. The stereo decoder receives the stereo multiplexed signal and the PLL output signal to separate a left channel signal and a right channel signal from the stereo multiplexed signal.
    Type: Grant
    Filed: July 12, 2006
    Date of Patent: October 26, 2010
    Assignee: Mediatek Inc.
    Inventors: Hsiang-Hui Chang, Chih-Chien Huang, Chieh Hung Chen
  • Patent number: 7697908
    Abstract: A FM receiver comprises an IF filter, a demodulator and a decoder. The IF filter generates an RSSI and a FM modulated signal in response to a FM signal. The demodulator comprises a duty-to-voltage amplifier for amplifying a peak of a MPX signal. The duty-to-voltage amplifier comprises a current source, a switch and a current splitter. The current source generates a current. The switch controls a flow of the first current in response to a PWM signal. The current splitter splits the flow of the current into a sub-flow in response to the RSSI. The peak of the MPX signal is proportional to the sub-flow. The decoder receives the MPX signal to generate an audio signal to play sound.
    Type: Grant
    Filed: April 13, 2006
    Date of Patent: April 13, 2010
    Assignee: Mediatek Inc.
    Inventors: Hsiang-Hui Chang, Chieh Hung Chen
  • Publication number: 20090252337
    Abstract: A multi-channel decoding method includes: receiving an input signal to generate a first channel output signal and a second channel output signal, wherein the input signal is mixed with a specific clock signal; and gradually changing an amplitude of the specific clock signal from a first value to a second value when switching from a first mode corresponding to a first number of channels to a second mode corresponding to a second number of channels. Systems utilizing the method and another method further comprising calibration are also disclosed.
    Type: Application
    Filed: April 8, 2008
    Publication date: October 8, 2009
    Inventors: Chieh-Hung Chen, Tsung-Ling Li, Chia-Huang Fu
  • Publication number: 20090233566
    Abstract: A calibration circuit for calibrating an output level of a demodulator includes a test signal generator, an RSSI module and a calibration module. The test signal generator generates a test signal, and the RSSI module detects the test signal to generate a control signal, wherein the control signal controls the demodulator to process the test signal to generate a determined output signal. The calibration module then calibrates the RSSI module according to the output signal in order to calibrate the output level of the demodulator. When the control signal is utilized to selectively enable or disable a soft-mute function of the demodulator, the calibration module can be utilized to calibrate or determine the soft-mute function of the demodulator.
    Type: Application
    Filed: March 11, 2008
    Publication date: September 17, 2009
    Inventors: Tsung-Ling Li, Hsiang-Hui Chang, Chia-Huang Fu, En-Hsiang Yeh, Hsueh-Kun Liao, Chieh-Hung Chen
  • Publication number: 20090232316
    Abstract: A multi-channel blend system includes a calibration circuit and a decoding circuit having a gain amplifying module. The decoding circuit is utilized for receiving an input signal to generate a first channel output signal and a second channel output signal. The gain amplifying module is utilized for providing a gain value for determining a separation ratio between the first channel output signal and the second channel output signal according to a calibration signal. The calibration circuit is utilized for providing a predetermined test signal serving as the input signal so as to generate the calibration signal according to at least one of the first and second channel output signals generated from the predetermined test signal.
    Type: Application
    Filed: March 14, 2008
    Publication date: September 17, 2009
    Inventor: Chieh-Hung Chen
  • Publication number: 20090156146
    Abstract: A FM receiver comprises an IF filter, a demodulator and a decoder. The IF filter generates an RSSI and a FM modulated signal in response to a FM signal. The demodulator comprises a duty-to-voltage amplifier for amplifying a peak of a MPX signal. The duty-to-voltage amplifier comprises a current source, a switch and a current splitter. The current source generates a current. The switch controls a flow of the first current in response to a PWM signal. The current splitter splits the flow of the current into a sub-flow in response to the RSSI. The peak of the MPX signal is proportional to the sub-flow. The decoder receives the MPX signal to generate an audio signal to play sound.
    Type: Application
    Filed: February 17, 2009
    Publication date: June 18, 2009
    Applicant: MEDIATEK INC.
    Inventors: Hsiang-Hui CHANG, Chieh Hung CHEN
  • Publication number: 20080013743
    Abstract: A stereo decoding system comprises an oscillator, a bandpass filter, a PLL unit and a stereo decoder. The oscillator generates a first signal with a center frequency. The bandpass filter receives a stereo multiplexed signal and the first signal to filter out a pilot signal. The PLL unit receives the pilot signal to generate a PLL output signal. The stereo decoder receives the stereo multiplexed signal and the PLL output signal to separate a left channel signal and a right channel signal from the stereo multiplexed signal.
    Type: Application
    Filed: July 12, 2006
    Publication date: January 17, 2008
    Applicant: MEDIATEK INC.
    Inventors: Hsiang-Hui Chang, Chih-Chien Huang, Chieh Hung Chen
  • Patent number: 7142138
    Abstract: The present invention discloses an on-line calibration method, which utilizes two calibration algorithms running in the background without interrupting the normal operation of the analog signal process. The method includes performing a residue amplifier gain error calibration and performing a DAC non-linearity calibration. The residue amplifier gain error calibration can reduce the gain error of the residue amplifier for a missing code or a missing decision level phenomenon. The DAC non-linearity calibration can relax the matching requirement of passive components in current semiconductor processes. The present invention discloses a two-step ADC (Analog-to-Digital Converter), which includes a first signal processing unit, a second signal processing unit, a programmable gain control unit and a programmable reference voltage generator, performing the on-line calibration method.
    Type: Grant
    Filed: August 12, 2005
    Date of Patent: November 28, 2006
    Assignee: National Tsing Hua University
    Inventors: Chieh-Hung Chen, Yi-Chung Chen, Po-Chiun Huang
  • Patent number: D838716
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: January 22, 2019
    Assignee: Lite-On Technology Corporation
    Inventors: Jun-Wen Teng, Chieh-Hung Chen