Patents by Inventor Chieh-Ning Feng
Chieh-Ning Feng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240120207Abstract: A semiconductor package includes a die having a plurality of devices over a first substrate, where the first substrate includes a dopant at a first concentration and the first substrate has a first width along a horizontal direction. The semiconductor package further includes a second substrate fused with the first substrate, where the second substrate includes the dopant at a second concentration greater than the first concentration.Type: ApplicationFiled: February 15, 2023Publication date: April 11, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Lung-Kai Mao, Wen-Hsiung Lu, Pei-Wei Lee, Szu-Hsien Lee, Chieh-Ning Feng
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Publication number: 20230343783Abstract: A semiconductor device includes a first semiconductor fin and a second semiconductor fin extending along a first direction. The semiconductor device includes a dielectric fin, extending along the first direction, that is disposed between the first and second semiconductor fins. The semiconductor device includes a gate isolation structure vertically disposed above the dielectric fin. The semiconductor device includes a metal gate layer extending along a second direction perpendicular to the first direction, wherein the metal gate layer includes a first portion straddling the first semiconductor fin and a second portion straddling the second semiconductor fin. The gate isolation structure has a central portion and one or more side portions, the central portion extends toward the dielectric fin a further distance than at least one of the one or more side portions.Type: ApplicationFiled: June 30, 2023Publication date: October 26, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ya-Yi Tsai, Wen-Shuo Hsieh, Shu-Yuan Ku, Chieh-Ning Feng
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Patent number: 11715736Abstract: A semiconductor device includes a first semiconductor fin and a second semiconductor fin extending along a first direction. The semiconductor device includes a dielectric fin, extending along the first direction, that is disposed between the first and second semiconductor fins. The semiconductor device includes a gate isolation structure vertically disposed above the dielectric fin. The semiconductor device includes a metal gate layer extending along a second direction perpendicular to the first direction, wherein the metal gate layer includes a first portion straddling the first semiconductor fin and a second portion straddling the second semiconductor fin. The gate isolation structure has a central portion and one or more side portions, the central portion extends toward the dielectric fin a further distance than at least one of the one or more side portions.Type: GrantFiled: June 23, 2021Date of Patent: August 1, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ya-Yi Tsai, Wen-Shuo Hsieh, Shu-Yuan Ku, Chieh-Ning Feng
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Publication number: 20230063087Abstract: A method includes forming a first, second, third, fourth, fifth, and sixth fin structure. The second fin structure is separated from each of the first and third fin structures by a first distance, the fifth fin structure is separated from each of the fourth and sixth fin structures by the first distance, and the third fin structure is separated from the fourth fin structure by a second distance greater than the first distance. The method includes forming a first dummy gate structure overlaying the first through third fin structures, and a second dummy gate structure overlaying the fourth through sixth fin structures; forming a number of source/drain structures that are coupled to the first, second, third, fourth, fifth, and sixth fin structures, respectively; and replacing the third fin structure with a first dielectric structure, and replacing the fourth fin structure with a second dielectric structure.Type: ApplicationFiled: August 27, 2021Publication date: March 2, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Yao Lin, Chen-Ping Chen, Chieh-Ning Feng, Hsiao Wen Lee, Chih-Han Lin
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Publication number: 20230061497Abstract: A method includes forming a dielectric fin over a substrate between a first semiconductor fin and a second semiconductor fin. The first and second semiconductor fins, and the dielectric fin all extend along a first lateral direction. The method includes forming a dummy gate structure that extends along a second lateral direction and includes a first portion and a second portion. The first and second portions overlay the first and second semiconductor fins, respectively, and separate from each other with the dielectric fin. The method includes removing upper sidewall portions of the dielectric fin. The method includes replacing the first and second portions of the dummy gate structure with a first and second active gate structures, respectively.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Yao LIN, Chieh-Ning Feng, Hsiao Wen Lee, Ming-Ching Chang
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Publication number: 20230066828Abstract: A semiconductor device includes a substrate; a semiconductor fin structure disposed over the substrate, wherein the semiconductor fin structure extend along a first lateral direction; a gate structure that straddles a semiconductor fin structure, wherein the gate structure extends along a second lateral direction, the first lateral direction perpendicular to the second lateral direction; a dielectric fin structure that extends along the first lateral direction and is disposed next to the semiconductor structure fin structure; and a gate isolation structure disposed above the dielectric fin structure. The gate isolation structure contacts an upper portion of the gate structure at a first tilted interface.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shu-Uei Jang, Shih-Yao Lin, Chieh-Ning Feng, Shu-Yuan Ku
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Publication number: 20230067859Abstract: A semiconductor device includes a plurality of first channel layers vertically spaced from one another and a plurality of second channel layers vertically spaced form one another. Each of the plurality of first and second channel layers extend along a first lateral direction. The semiconductor device includes an isolation structure disposed between the plurality of first channel layers and the plurality of second channel layers along a second lateral direction perpendicular to the first lateral direction. The semiconductor device includes a plurality of inner spacers discretely disposed along a first sidewall of the isolation structure that faces toward the first lateral direction, or discretely disposed along a second sidewall of the isolation structure that faces away from the first lateral direction wherein an interface between each of the plurality of inner spacers and the first or second sidewall has a vertical profile.Type: ApplicationFiled: February 15, 2022Publication date: March 2, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Yao Lin, Chieh-Ning Feng, Hsiaowen Lee, Ming-Ching Chang
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Publication number: 20220415886Abstract: A semiconductor device includes a first semiconductor fin and a second semiconductor fin extending along a first direction. The semiconductor device includes a dielectric fin, extending along the first direction, that is disposed between the first and second semiconductor fins. The semiconductor device includes a gate isolation structure vertically disposed above the dielectric fin. The semiconductor device includes a metal gate layer extending along a second direction perpendicular to the first direction, wherein the metal gate layer includes a first portion straddling the first semiconductor fin and a second portion straddling the second semiconductor fin. The gate isolation structure has a central portion and one or more side portions, the central portion extends toward the dielectric fin a further distance than at least one of the one or more side portions.Type: ApplicationFiled: June 23, 2021Publication date: December 29, 2022Applicant: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: YA-YI TSAI, Wen-Shuo Hsieh, Shu-Yuan Ku, Chieh-Ning Feng
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Publication number: 20220384271Abstract: A method of forming a semiconductor device includes forming a first fin and a second fin protruding above a substrate; forming isolation regions on opposing sides of the first fin and the second fin; forming a metal gate over the first fin and over the second fin, the metal gate being surrounded by a first dielectric layer; and forming a recess in the metal gate between the first fin and the second fin, where the recess extends from an upper surface of the metal gate distal the substrate into the metal gate, where the recess has an upper portion distal the substrate and a lower portion between the upper portion and the substrate, where the upper portion has a first width, and the lower portion has a second width larger than the first width, the first width and the second width measured along a longitudinal direction of the metal gate.Type: ApplicationFiled: August 9, 2022Publication date: December 1, 2022Inventors: Chih-Chang Hung, Chieh-Ning Feng, Chun-Liang Lai, Yih-Ann Lin, Ryan Chia-Jen Chen
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Patent number: 11495501Abstract: A method of forming a semiconductor device includes forming a first fin and a second fin protruding above a substrate; forming isolation regions on opposing sides of the first fin and the second fin; forming a metal gate over the first fin and over the second fin, the metal gate being surrounded by a first dielectric layer; and forming a recess in the metal gate between the first fin and the second fin, where the recess extends from an upper surface of the metal gate distal the substrate into the metal gate, where the recess has an upper portion distal the substrate and a lower portion between the upper portion and the substrate, where the upper portion has a first width, and the lower portion has a second width larger than the first width, the first width and the second width measured along a longitudinal direction of the metal gate.Type: GrantFiled: February 5, 2021Date of Patent: November 8, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Chang Hung, Chieh-Ning Feng, Chun-Liang Lai, Yih-Ann Lin, Ryan Chia-Jen Chen
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Publication number: 20220293594Abstract: A semiconductor device includes a dielectric fin between a first semiconductor channel and a second semiconductor channel. The semiconductor device includes a first gate structure. The first gate structure includes a first portion and a second portion separated from each other by the dielectric fin. The semiconductor device includes a first gate spacer that extends along sidewalls of the first portion of the first gate structure. The semiconductor device includes a second gate spacer that extends along sidewalls of the second portion of the first gate structure, respectively. At least one of the first gate spacer or second gate spacer has a first portion with a first thickness and a second portion with a second thickness less than the first thickness, and wherein the first portion is closer to the dielectric fin than the second portion.Type: ApplicationFiled: March 12, 2021Publication date: September 15, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Yao Lin, Chieh-Ning Feng, Hsiao Wen Lee, Chao-Cheng Chen
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Patent number: 11145752Abstract: A method includes forming a gate dielectric layer, forming a metal gate strip over a bottom portion of the gate dielectric layer, and performing a first etching process on the metal gate strip to remove a portion of the metal gate strip. The first etching process is performed anisotropically. After the first etching process, a second etching process is performed on the metal gate strip to remove a residue portion of the metal gate strip. The second etching process includes an isotropic etching process. A dielectric material is filled into a recess left by the etched portion and the etched residue portion of the metal gate strip.Type: GrantFiled: September 17, 2019Date of Patent: October 12, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chieh-Ning Feng, Chih-Chang Hung, Bing-Hung Chen, Yih-Ann Lin
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Publication number: 20210159123Abstract: A method of forming a semiconductor device includes forming a first fin and a second fin protruding above a substrate; forming isolation regions on opposing sides of the first fin and the second fin; forming a metal gate over the first fin and over the second fin, the metal gate being surrounded by a first dielectric layer; and forming a recess in the metal gate between the first fin and the second fin, where the recess extends from an upper surface of the metal gate distal the substrate into the metal gate, where the recess has an upper portion distal the substrate and a lower portion between the upper portion and the substrate, where the upper portion has a first width, and the lower portion has a second width larger than the first width, the first width and the second width measured along a longitudinal direction of the metal gate.Type: ApplicationFiled: February 5, 2021Publication date: May 27, 2021Inventors: Chih-Chang Hung, Chieh-Ning Feng, Chun-Liang Lai, Yih-Ann Lin, Ryan Chia-Jen Chen
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Publication number: 20210083072Abstract: A method includes forming a gate dielectric layer, forming a metal gate strip over a bottom portion of the gate dielectric layer, and performing a first etching process on the metal gate strip to remove a portion of the metal gate strip. The first etching process is performed anisotropically. After the first etching process, a second etching process is performed on the metal gate strip to remove a residue portion of the metal gate strip. The second etching process includes an isotropic etching process. A dielectric material is filled into a recess left by the etched portion and the etched residue portion of the metal gate strip.Type: ApplicationFiled: September 17, 2019Publication date: March 18, 2021Inventors: Chieh-Ning Feng, Chih-Chang Hung, Bing-Hung Chen, Yih-Ann Lin
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Patent number: 10916477Abstract: A method of forming a semiconductor device includes forming a first fin and a second fin protruding above a substrate; forming isolation regions on opposing sides of the first fin and the second fin; forming a metal gate over the first fin and over the second fin, the metal gate being surrounded by a first dielectric layer; and forming a recess in the metal gate between the first fin and the second fin, where the recess extends from an upper surface of the metal gate distal the substrate into the metal gate, where the recess has an upper portion distal the substrate and a lower portion between the upper portion and the substrate, where the upper portion has a first width, and the lower portion has a second width larger than the first width, the first width and the second width measured along a longitudinal direction of the metal gate.Type: GrantFiled: January 15, 2019Date of Patent: February 9, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Chang Hung, Chieh-Ning Feng, Chun-Liang Lai, Yih-Ann Lin, Ryan Chia-Jen Chen
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Publication number: 20200105613Abstract: A method of forming a semiconductor device includes forming a first fin and a second fin protruding above a substrate; forming isolation regions on opposing sides of the first fin and the second fin; forming a metal gate over the first fin and over the second fin, the metal gate being surrounded by a first dielectric layer; and forming a recess in the metal gate between the first fin and the second fin, where the recess extends from an upper surface of the metal gate distal the substrate into the metal gate, where the recess has an upper portion distal the substrate and a lower portion between the upper portion and the substrate, where the upper portion has a first width, and the lower portion has a second width larger than the first width, the first width and the second width measured along a longitudinal direction of the metal gate.Type: ApplicationFiled: January 15, 2019Publication date: April 2, 2020Inventors: Chih-Chang Hung, Chieh-Ning Feng, Chun-Liang Lai, Yih-Ann Lin, Ryan Chia-Jen Chen