Patents by Inventor Chieh-Sheng Tu

Chieh-Sheng Tu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11967510
    Abstract: A heating circuit is provided. The heating circuit is disposed in a chip which has a normal operation temperature range. The heating circuit includes a comparison circuit and a thermal-energy generation circuit. The comparison circuit compares a temperature voltage with a first threshold voltage. The temperature voltage represents a temperature of the chip. The thermal-energy generation circuit is controlled by the comparison circuit. When the temperature voltage is less than the first threshold voltage, the comparison circuit enables the thermal-energy generation circuit to generate thermal energy to raise the temperature of the chip.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: April 23, 2024
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventors: Wei-Hang Chiu, Chieh-Sheng Tu
  • Publication number: 20240106433
    Abstract: A touch detection circuit detects whether a key is being touched and includes a comparator, a compensation capacitor, and a voltage control circuit. The comparator includes an inverting input, a non-inverting input, and an output terminal. The compensation capacitor is coupled to the inverting input. The voltage control circuit provides an output voltage to the non-inverting input. In a calibration mode, the voltage control circuit adjusts the output voltage according to the voltage level of the output terminal.
    Type: Application
    Filed: May 22, 2023
    Publication date: March 28, 2024
    Inventors: Fu-Chiang CHUANG, Chieh-Sheng TU
  • Publication number: 20240069583
    Abstract: A control circuit including a storage circuit, a voltage detection circuit, a processing circuit, and a wake-up circuit is provided. The storage circuit includes a register and stores a program code. The voltage detection circuit detects an external voltage. The processing circuit accesses the register in response to the external voltage reaching a first predetermined voltage. The processing circuit enters a power-down mode in response to the external voltage reaching a second predetermined voltage. In the power-down mode, the processing circuit stops accessing the register. The wake-up circuit determines whether a wake-up event occurs. In response to the wake-up event, the wake-up circuit directs the processing circuit to exit the power-down mode and enter an operation mode. In response to there being no wake-up event, the processing circuit stays in the power-down mode. In the operation mode, the processing circuit executes the program code.
    Type: Application
    Filed: April 27, 2023
    Publication date: February 29, 2024
    Inventors: Chieh-Sheng TU, Te-Tsoung TSAI, Ta-Chin CHIU
  • Publication number: 20240045826
    Abstract: A micro controller unit coupled between a master device and a slave device and including a first communication interface, a serial peripheral interface (SPI) circuit, a switch circuit, a second communication interface, and a switching control circuit is provided. The first communication interface receives a first external signal provided by the master device. The SPI circuit is configured to generate an internal signal. The switch circuit uses a second external signal or the internal signal as an output signal according to a control signal. The second communication interface provides the output signal to the slave device. The switching control circuit generates the control signal according to the level of the first external signal.
    Type: Application
    Filed: May 18, 2023
    Publication date: February 8, 2024
    Inventors: Chieh-Sheng TU, Ta-Chin CHIU
  • Publication number: 20240028807
    Abstract: An embodiment of the present disclosure provides an online integrated microcontroller development tool system. Through the present disclosure, a microcontroller block of a suitable model number is selected according to a client requirement, pins of the microcontroller may be arranged, the microcontroller block with the arranged have been pins is connected to a functional component selected by the client, a corresponding circuit structure is generated, and based on the circuit structure, a microcontroller system hardware description code is generated and output. Different from the conventional development platform, the present disclosure helps clients to develop microcontroller application circuits for different applications through a pin required module, a functional component module and a description code project output module. Thus, purposes of simple operation and saving development time can be achieved.
    Type: Application
    Filed: January 10, 2023
    Publication date: January 25, 2024
    Inventors: CHIEH-SHENG TU, TA-CHIN CHIU, CHUN-MING HUANG, JEN-CHIH LIU
  • Patent number: 11789509
    Abstract: An electronic device is provided. The electronic device includes a power pin, a main circuit, and a start-up circuit. The power pin is configured to receive a power supply. The start-up circuit includes a switch coupled between the power pin and the main circuit, a timer and an oscillator. The switch is configured to selectively provide the power supply to the main circuit in response to a control signal. The oscillator, is configured to provide a periodic signal. The timer is configured to provide the control signal to turn on the switch when counting to a start-up time according to the periodic signal, so that the main circuit is configured to provide a fixed voltage according to the power supply.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: October 17, 2023
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventors: Chun-Ming Huang, Chieh-Sheng Tu
  • Patent number: 11764769
    Abstract: A control circuit and method for detecting a glitch signal on a bus are provided. The control circuit includes: input ends, respectively receiving a data signal and a clock signal from the bus; a counter, for calculating a time or a number of times in a low level period of the clock signal; a comparator, receiving an output of the time counted by the counter and a threshold value, and generating a comparison result by comparing the time and the threshold value; and an error detector, coupled to the comparator to receive the comparison result, and generating an error flag. When the comparison result indicates that there is a level change during the low level period of the clock signal, the error detector generates an error flag.
    Type: Grant
    Filed: July 7, 2022
    Date of Patent: September 19, 2023
    Assignee: Nuvoton Technology Corporation
    Inventors: Ta-Chin Chiu, Chieh-Sheng Tu
  • Patent number: 11698875
    Abstract: An IC is provided. The IC includes an input pin, a controller, a timer, a first memory, a processor, at least one output pin, an output module coupled to the output pin, and a direct memory access (DMA) device coupled between the output module and the first memory. The controller is configured to provide a first control signal in response to a command from the input pin. The timer is configured to periodically provide a trigger signal according to the first control signal. The processor is configured to store first data in the first memory. The DMA device is configured to obtain the first data from the first memory in response to the trigger signal, and transmit the first data to the output module. The output module is configured to provide the first data to the output pin according to a transmission rate.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: July 11, 2023
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventors: Chieh-Sheng Tu, Ta-Chin Chiu
  • Publication number: 20220374373
    Abstract: An IC is provided. The IC includes an input pin, a controller, a timer, a first memory, a processor, at least one output pin, an output module coupled to the output pin, and a direct memory access (DMA) device coupled between the output module and the first memory. The controller is configured to provide a first control signal in response to a command from the input pin. The timer is configured to periodically provide a trigger signal according to the first control signal. The processor is configured to store first data in the first memory. The DMA device is configured to obtain the first data from the first memory in response to the trigger signal, and transmit the first data to the output module. The output module is configured to provide the first data to the output pin according to a transmission rate.
    Type: Application
    Filed: October 26, 2021
    Publication date: November 24, 2022
    Inventors: Chieh-Sheng TU, Ta-Chin CHIU
  • Publication number: 20220334627
    Abstract: An electronic device is provided. The electronic device includes a power pin, a main circuit, and a start-up circuit. The power pin is configured to receive a power supply. The start-up circuit includes a switch coupled between the power pin and the main circuit, a timer and an oscillator. The switch is configured to selectively provide the power supply to the main circuit in response to a control signal. The oscillator, is configured to provide a periodic signal. The timer is configured to provide the control signal to turn on the switch when counting to a start-up time according to the periodic signal, so that the main circuit is configured to provide a fixed voltage according to the power supply.
    Type: Application
    Filed: September 15, 2021
    Publication date: October 20, 2022
    Inventors: Chun-Ming HUANG, Chieh-Sheng TU
  • Publication number: 20210202279
    Abstract: A heating circuit is provided. The heating circuit is disposed in a chip which has a normal operation temperature range. The heating circuit includes a comparison circuit and a thermal-energy generation circuit. The comparison circuit compares a temperature voltage with a first threshold voltage. The temperature voltage represents a temperature of the chip. The thermal-energy generation circuit is controlled by the comparison circuit. When the temperature voltage is less than the first threshold voltage, the comparison circuit enables the thermal-energy generation circuit to generate thermal energy to raise the temperature of the chip.
    Type: Application
    Filed: September 30, 2020
    Publication date: July 1, 2021
    Inventors: Wei-Hang CHIU, Chieh-Sheng TU
  • Publication number: 20210156744
    Abstract: A built-in temperature sensing device of a single chip includes a built-in temperature sensor and a temperature comparator. The built-in temperature sensor senses a single chip temperature of the single chip. The temperature comparator receives the single chip temperature and a threshold temperature, and compares the single chip temperature with the threshold temperature to generate an output signal to take a necessary protection method.
    Type: Application
    Filed: September 30, 2020
    Publication date: May 27, 2021
    Inventor: Chieh-Sheng TU
  • Patent number: 10976768
    Abstract: A clock adjusting device includes an oscillator, a first counter, a second counter, a count comparator and a threshold comparator. The oscillator transmits an operation clock signal. The first counter counts a reference clock signal, to obtain a reference clock count value. The second counter counts the operation clock signal to obtain an operation clock count value. The count comparator compares the reference clock count value with the operation clock count value, to obtain a candidate correction value. The oscillator adjusts the operation clock signal according to an output correction value. The threshold comparator compares the candidate correction value and an updated threshold. When the candidate correction value is lower than the updated threshold, the candidate correction value is used as the output correction value, and when the candidate correction value exceeds the updated threshold, a current correction value is used as the output connection value.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: April 13, 2021
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventors: Chang-Hong Lin, Chieh-Sheng Tu
  • Patent number: 10826474
    Abstract: A clock generation circuit and a clock adjustment method thereof are provided. The clock generation circuit includes a fixed clock source, a variable clock source, a timing adjustment circuit, and a pulse width signal generator. The fixed clock source generates a reference clock signal having a fixed frequency. The variable clock source receives a frequency setting signal to correspondingly generate an operational clock signal having a variable frequency. The timing adjustment circuit determines whether a frequency of the operation clock signal is N times of a target frequency according to the reference clock signal to set a frequency of the operation clock signal. The pulse width signal generator divides the operating clock signal to generate a pulse width modulation signal having the target frequency.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: November 3, 2020
    Assignee: Nuvoton Technology Corporation
    Inventors: Ta-Chin Chiu, Chieh-Sheng Tu
  • Publication number: 20200136597
    Abstract: A clock generation circuit and a clock adjustment method thereof are provided. The clock generation circuit includes a fixed clock source, a variable clock source, a timing adjustment circuit, and a pulse width signal generator. The fixed clock source generates a reference clock signal having a fixed frequency. The variable clock source receives a frequency setting signal to correspondingly generate an operational clock signal having a variable frequency. The timing adjustment circuit determines whether a frequency of the operation clock signal is N times of a target frequency according to the reference clock signal to set a frequency of the operation clock signal. The pulse width signal generator divides the operating clock signal to generate a pulse width modulation signal having the target frequency.
    Type: Application
    Filed: October 23, 2019
    Publication date: April 30, 2020
    Applicant: Nuvoton Technology Corporation
    Inventors: Ta-Chin Chiu, Chieh-Sheng Tu
  • Publication number: 20200103931
    Abstract: A clock adjusting device includes an oscillator, a first counter, a second counter, a count comparator and a threshold comparator. The oscillator transmits an operation clock signal. The first counter counts a reference clock signal, to obtain a reference clock count value. The second counter counts the operation clock signal to obtain an operation clock count value. The count comparator compares the reference clock count value with the operation clock count value, to obtain a candidate correction value. The oscillator adjusts the operation clock signal according to an output correction value. The threshold comparator compares the candidate correction value and an updated threshold. When the candidate correction value is lower than the updated threshold, the candidate correction value is used as the output correction value, and when the candidate correction value exceeds the updated threshold, a current correction value is used as the output connection value.
    Type: Application
    Filed: September 27, 2019
    Publication date: April 2, 2020
    Inventors: Chang-Hong Lin, Chieh-Sheng Tu
  • Patent number: 9870826
    Abstract: A memory apparatus and a data access method thereof are provided. The memory apparatus includes a first memory unit and a second memory unit, wherein an access speed of the second memory unit is higher than an access speed of the first memory unit. The method includes: receiving write data and a corresponding write address; comparing the write data with data corresponding to the write address in the second memory unit, so as to determine whether to write the write data into a current physical memory page of the first memory unit and into the second memory unit; after a data writing operation is executed, executing a data arranging operation on the current physical memory page according to the data in the second memory unit when the current physical memory page is full; and when a read command is received, reading the corresponding data in the second memory unit.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: January 16, 2018
    Assignee: Nuvoton Technology Corporation
    Inventors: Chang-Hong Lin, Chun-Hao Huang, Chieh-Sheng Tu
  • Publication number: 20170229182
    Abstract: A memory apparatus and a data access method thereof are provided. The memory apparatus includes a first memory unit and a second memory unit, wherein an access speed of the second memory unit is higher than an access speed of the first memory unit. The method includes: receiving write data and a corresponding write address; comparing the write data with data corresponding to the write address in the second memory unit, so as to determine whether to write the write data into a current physical memory page of the first memory unit and into the second memory unit; after a data writing operation is executed, executing a data arranging operation on the current physical memory page according to the data in the second memory unit when the current physical memory page is full; and when a read command is received, reading the corresponding data in the second memory unit.
    Type: Application
    Filed: May 12, 2016
    Publication date: August 10, 2017
    Inventors: Chang-Hong Lin, Chun-Hao Huang, Chieh-Sheng Tu
  • Patent number: 8139086
    Abstract: The invention provides an image processing method. An image is provided, and the image is divided into a first subimage, a second subimage, a third subimage, and a fourth subimage according to a decomposing method. Next, the first, second, third, and fourth subimages are processed to generate a first subframe, a second subframe, a third subframe, and a fourth subframe. Finally, the first, second, third, and fourth subframes are combined as a frame according to a composing method corresponding to the decomposing method.
    Type: Grant
    Filed: May 8, 2008
    Date of Patent: March 20, 2012
    Assignee: Nuvoton Technology Corporation
    Inventors: Chieh-Sheng Tu, Chung-Hsin Chen, Nai-Wen Cheng, Chun-Min Chen, Chi-Chuang Hsu
  • Patent number: 8130232
    Abstract: A drawing control method, a drawing control apparatus, and a drawing control system for embedded system are provided. The present invention adopts an independent drawing control apparatus to control a drawing unit to draw a frame, and move the drawn frame to an external frame buffer in advance, and therefore the number of lines that can be drawn is not restricted by the capacity of the memory of the drawing unit. Further, the present invention employs a counter to accumulate a counting number upon each time completion of drawing frame or moving frame. Whenever the counting number is accumulated, the drawing unit is controlled to perform a next stage of frame drawing or frame moving. In this concern, the present invention eliminates the time for external accessing, and thus achieving parallel processing, and instant displaying.
    Type: Grant
    Filed: June 17, 2008
    Date of Patent: March 6, 2012
    Assignee: Nuvoton Technology Corporation
    Inventors: Chung-Hsin Chen, Chieh-Sheng Tu, Tien-Der Yeh, Chi-Chuang Hsu, Che-Wei Chang