Abstract: A metal-insulator-metal (MIM) capacitor structure and method for forming MIM capacitor structure are provided. The MIM capacitor structure includes a substrate and a metal-insulator-metal (MIM) capacitor formed on the substrate. The MIM capacitor includes a capacitor top metal (CTM) layer, a capacitor bottom metal (CBM) layer and an insulator formed between the CTM layer and the CBM layer. The insulator includes an insulating layer and a first high-k dielectric layer, and the insulating layer includes a nitride layer and an oxide layer, and the nitride layer is formed between the first high-k dielectric layer and the oxide layer.

Abstract: In a method for manufacturing a semiconductor device, a substrate including a gate structure is provided. A source region and a drain region are formed at opposing sides of the gate structure and an implant region for a resistor device is formed in the substrate. Pocket implant regions are formed in the source region and the drain region. A dielectric layer is formed to cover the gate structure and the substrate. A portion of dopants in the pocket implant regions interact with portions of dopants in the source region and the drain region to form lightly doped drain regions above the pocket implant regions. A resistor region of the resistor device is defined on the implant region. A portion of the dielectric layer is removed to form a spacer on a sidewall of the gate structure and a resistor protection dielectric layer on a portion of the implant region.

Abstract: Embodiments of mechanisms for forming a metal-insulator-metal (MIM) capacitor structure are provided. The metal-insulator-metal capacitor structure includes a substrate. The MIM capacitor structure also includes a CBM layer formed on the substrate, and the CBM layer includes a bottom barrier layer, a main metal layer and a top barrier layer. The MIM capacitor structure further includes a first high-k dielectric layer formed on the CBM layer, an insulating layer formed on the first high-k dielectric layer and a second high-k dielectric layer formed on the insulating layer. The MIM capacitor structure also includes a CTM layer formed on the second high-k dielectric layer, and the CBM layer includes a bottom barrier layer, a main metal layer and a top barrier layer.

Abstract: In a method for manufacturing a semiconductor device, a substrate including a gate structure is provided. A source region and a drain region are formed at opposing sides of the gate structure and an implant region for a resistor device is formed in the substrate. Pocket implant regions are formed in the source region and the drain region. A dielectric layer is formed to cover the gate structure and the substrate. A portion of dopants in the pocket implant regions interact with portions of dopants in the source region and the drain region to form lightly doped drain regions above the pocket implant regions. A resistor region of the resistor device is defined on the implant region. A portion of the dielectric layer is removed to form a spacer on a sidewall of the gate structure and a resistor protection dielectric layer on a portion of the implant region.

Abstract: A metal-insulator-metal (MIM) capacitor structure and method for forming MIM capacitor structure are provided. The MIM capacitor structure includes a substrate and a metal-insulator-metal (MIM) capacitor formed on the substrate. The MIM capacitor includes a capacitor top metal (CTM) layer, a capacitor bottom metal (CBM) layer and an insulator formed between the CTM layer and the CBM layer. The insulator includes an insulating layer and a first high-k dielectric layer, and the insulating layer includes a nitride layer and an oxide layer, and the nitride layer is formed between the first high-k dielectric layer and the oxide layer.

Abstract: Embodiments of mechanisms for forming a metal-insulator-metal (MIM) capacitor structure are provided. The metal-insulator-metal capacitor structure includes a substrate. The MIM capacitor structure also includes a CBM layer formed on the substrate, and the CBM layer includes a bottom barrier layer, a main metal layer and a top barrier layer. The MIM capacitor structure further includes a first high-k dielectric layer formed on the CBM layer, an insulating layer formed on the first high-k dielectric layer and a second high-k dielectric layer formed on the insulating layer. The MIM capacitor structure also includes a CTM layer formed on the second high-k dielectric layer, and the CBM layer includes a bottom barrier layer, a main metal layer and a top barrier layer.

Abstract: A structure of a DRAM cylindrical capacitor includes a substrate, a dielectric layer, an amorphous silicon spacer, a polysilicon plug, a HSG layer, a conductive layer and a capacitor dielectric layer. The dielectric layer is disposed on the substrate and includes an opening. The amorphous silicon spacer is disposed on the sidewall of the opening, wherein the polysilicon plug is exposed by the opening. The polysilicon plug includes a notch, and the internal surface of the notch is at the same plane as the internal surface of the amorphous silicon spacer. The HSG layer is disposed on the surface of the amorphous silicon spacer. Furthermore, the conductive layer is disposed on the HSG layer and the capacitor dielectric layer is disposed between the HSG layer and the conductive layer.

Abstract: A structure of a DRAM cylindrical capacitor includes a substrate, a dielectric layer, an amorphous silicon spacer, a polysilicon plug, a HSG layer, a conductive layer and a capacitor dielectric layer. The dielectric layer is disposed on the substrate and includes an opening. The amorphous silicon spacer is disposed on the sidewall of the opening, wherein the polysilicon plug is exposed by the opening. The polysilicon plug includes a notch, and the internal surface of the notch is at the same plane as the internal surface of the amorphous silicon spacer. The HSG layer is disposed on the surface of the amorphous silicon spacer. Furthermore, the conductive layer is disposed on the HSG layer and the capacitor dielectric layer is disposed between the HSG layer and the conductive layer.

Abstract: A method of manufacturing dynamic random access memory (DRAM) cylindrical capacitor is provided. A substrate having a polysilicon plug formed therein is provided. A dielectric layer having an opening is disposed on the substrate, wherein the opening exposes the polysilicon plug. Thereafter, an amorphous silicon spacer is formed on the sidewall of the opening to expose a portion of the polysilicon plug. Next, a top portion of the exposed polysilicon plug is removed and a seeding method is used to grow a hemispherical silicon grain (HSG) layer on a surface of the amorphous silicon spacer. A capacitor dielectric layer is formed on the surface of the HSG layer and a conductive layer is then formed on the capacitor dielectric layer. As no HSG is formed on the polysilicon plug, and therefore the contact area of the capacitor is not decreased.

Abstract: A method of manufacturing a charge storage device is provided. Utilizing the capacity for a precise control of the thickness and the silicon content of a deposited film in an atomic layer deposition process, a stacked gradual material layer such as a hafnium silicon oxide (HfxSiyOz) layer is formed. The silicon content is gradually changed throughout the duration of the HfxSiyOz deposition process. The etching rate for the HfxSiyOz layer in dilute hydrogen fluoride solution is dependent on the silicon content y in the HfxSiyOz layer. The sidewalls of the stacked gradual material layer are etched to form an uneven profile. The lower electrode, the capacitor dielectric layer and the upper electrode are formed on the uneven sidewalls of the stacked gradual material layers, the area between the lower electrode and the upper electrode is increased to improve the capacitance of the charge storage device.

Abstract: A cylindrical capacitor comprising at least a substrate, a cylindrical bottom electrode, a structure layer, a top electrode and a capacitor dielectric layer is provided. The substrate has several plugs. The cylindrical bottom electrodes are disposed on the substrate and electrically connected to the respective plugs. The structure layer surrounds the periphery of each cylindrical bottom electrode. The structure layers that surround the two opposing cylindrical bottom electrodes have no mutual contact while the structure layers that surround two neighboring cylindrical bottom electrodes contact each other. Furthermore, the top electrodes cover the respective cylindrical bottom electrodes and the capacitor dielectric layer is disposed between each top electrode and corresponding cylindrical bottom electrode. Due to the structure layers, the mechanical strength of the whole cylindrical capacitor is improved and the density of the capacitor can be increased.

Abstract: A cylindrical capacitor comprising at least a substrate, a cylindrical bottom electrode, a structure layer, a top electrode and a capacitor dielectric layer is provided. The substrate has several plugs. The cylindrical bottom electrodes are disposed on the substrate and electrically connected to the respective plugs. The structure layer surrounds the periphery of each cylindrical bottom electrode. The structure layers that surround the two opposing cylindrical bottom electrodes have no mutual contact while the structure layers that surround two neighboring cylindrical bottom electrodes contact each other. Furthermore, the top electrodes cover the respective cylindrical bottom electrodes and the capacitor dielectric layer is disposed between each top electrode and corresponding cylindrical bottom electrode. Due to the structure layers, the mechanical strength of the whole cylindrical capacitor is improved and the density of the capacitor can be increased.

Abstract: A method of manufacturing a charge storage device is provided. Utilizing the capacity for a precise control of the thickness and the silicon content of a deposited film in an atomic layer deposition process, a stacked gradual material layer such as a hafnium silicon oxide (HfxSiyOz) layer is formed. The silicon content is gradually changed throughout the duration of the HfxSiyOz deposition process. The etching rate for the HfxSiyOz layer in dilute hydrogen fluoride solution is dependent on the silicon content y in the HfxSiyOz layer. The sidewalls of the stacked gradual material layer are etched to form an uneven profile. The lower electrode, the capacitor dielectric layer and the upper electrode are formed on the uneven sidewalls of the stacked gradual material layers, the area between the lower electrode and the upper electrode is increased to improve the capacitance of the charge storage device.

Abstract: A cylindrical capacitor comprising at least a substrate, a cylindrical bottom electrode, a structure layer, a top electrode and a capacitor dielectric layer is provided. The substrate has several plugs. The cylindrical bottom electrodes are disposed on the substrate and electrically connected to the respective plugs. The structure layer surrounds the periphery of each cylindrical bottom electrode. The structure layers that surround the two opposing cylindrical bottom electrodes have no mutual contact while the structure layers that surround two neighboring cylindrical bottom electrodes contact each other. Furthermore, the top electrodes cover the respective cylindrical bottom electrodes and the capacitor dielectric layer is disposed between each top electrode and corresponding cylindrical bottom electrode. Due to the structure layers, the mechanical strength of the whole cylindrical capacitor is improved and the density of the capacitor can be increased.

Abstract: A method of manufacturing dynamic random access memory (DRAM) cylindrical capacitor is provided. A substrate having a polysilicon plug formed therein is provided. A dielectric layer having an opening is disposed on the substrate, wherein the opening exposes the polysilicon plug. Thereafter, an amorphous silicon spacer is formed on the sidewall of the opening to expose a portion of the polysilicon plug. Next, a top portion of the exposed polysilicon plug is removed and a seeding method is used to grow a hemispherical silicon grain (HSG) layer on a surface of the amorphous silicon spacer. A capacitor dielectric layer is formed on the surface of the HSG layer and a conductive layer is then formed on the capacitor dielectric layer. As no HSG is formed on the polysilicon plug, and therefore the contact area of the capacitor is not decreased.