Patents by Inventor Chieh-Wen Lo

Chieh-Wen Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Selective Deposition of Thin Films with Improved Stability
    Publication number: 20240110284
    Abstract: A method of processing a substrate is disclosed which includes depositing a layer in a processing chamber on a field region, a sidewall region, and a fill region of a feature of the substrate, wherein a hardness of a portion of the layer deposited on the sidewall region is lower than a hardness of a portion of the layer deposited on the field region, and lower than a hardness of a portion of the layer deposited on the fill region.
    Type: Application
    Filed: September 26, 2023
    Publication date: April 4, 2024
    Inventors: Lulu XIONG, Kevin Hsiao, Chris LIU, Chieh-Wen LO, Sean M. SEUTTER, Deenesh PADHI, Prayudi LIANTO, Peng SUO, Guan Huei SEE, Zongbin WANG, Shengwei ZENG, Balamurugan RAMASAMY
  • Spatial semiconductor structure
    Patent number: 9362358
    Abstract: A method of fabricating a spatial semiconductor structure includes steps as follows. Firstly, a semiconductor substrate is provided. Then, a first mask layer is formed above the semiconductor substrate. Then, at least a first opening is formed in the first mask layer and exposes a portion of a surface of the semiconductor substrate. Then, a first semiconductor pattern is formed in the first opening. Then, a second mask layer is formed over the first semiconductor pattern and the first mask layer. Then, at least a second opening is formed through the second mask layer to the first mask layer and exposes another portion of the surface of the semiconductor substrate. And, a second semiconductor pattern is formed in the second opening.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: June 7, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Hung-Lin Shih, Chih-Chien Liu, Jei-Ming Chen, Wen-Yi Teng, Chieh-Wen Lo
  • GAP-FILLING DIELECTRIC LAYER METHOD FOR MANUFACTURING THE SAME AND APPLICATIONS THEREOF
    Publication number: 20160020139
    Abstract: A gap-filling dielectric layer, method for fabricating the same and applications thereof are disclosed. A silicon-containing dielectric layer is firstly deposited on a substrate. The silicon-containing dielectric layer is then subjected to a curing process, an in-situ wetting treatment and an annealing process in sequence, whereby a gap-filling dielectric layer with a nitrogen atom density less than 1×1022 atoms/cm3 is formed.
    Type: Application
    Filed: September 5, 2014
    Publication date: January 21, 2016
    Inventors: Wen-Yi Teng, Yuh-Min Lin, Chih-Chien Liu, Chieh-Wen Lo
  • SPATIAL SEMICONDUCTOR STRUCTURE
    Publication number: 20150311284
    Abstract: A method of fabricating a spatial semiconductor structure includes steps as follows. Firstly, a semiconductor substrate is provided. Then, a first mask layer is formed above the semiconductor substrate. Then, at least a first opening is formed in the first mask layer and exposes a portion of a surface of the semiconductor substrate. Then, a first semiconductor pattern is formed in the first opening. Then, a second mask layer is formed over the first semiconductor pattern and the first mask layer. Then, at least a second opening is formed through the second mask layer to the first mask layer and exposes another portion of the surface of the semiconductor substrate. And, a second semiconductor pattern is formed in the second opening.
    Type: Application
    Filed: July 7, 2015
    Publication date: October 29, 2015
    Inventors: Hung-Lin SHIH, Chih-Chien LIU, Jei-Ming CHEN, Wen-Yi TENG, Chieh-Wen LO
  • Spatial semiconductor structure and method of fabricating the same
    Patent number: 9105582
    Abstract: A method of fabricating a spatial semiconductor structure includes steps as follows. Firstly, a semiconductor substrate is provided. Then, a first mask layer is formed above the semiconductor substrate. Then, at least a first opening is formed in the first mask layer and exposes a portion of a surface of the semiconductor substrate. Then, a first semiconductor pattern is formed in the first opening. Then, a second mask layer is formed over the first semiconductor pattern and the first mask layer. Then, at least a second opening is formed through the second mask layer to the first mask layer and exposes another portion of the surface of the semiconductor substrate. And, a second semiconductor pattern is formed in the second opening.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: August 11, 2015
    Assignee: United Microelectronics Corporation
    Inventors: Hung-Lin Shih, Chih-Chien Liu, Jei-Ming Chen, Wen-Yi Teng, Chieh-Wen Lo
  • SPATIAL SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME
    Publication number: 20150048486
    Abstract: A method of fabricating a spatial semiconductor structure includes steps as follows. Firstly, a semiconductor substrate is provided. Then, a first mask layer is formed above the semiconductor substrate. Then, at least a first opening is formed in the first mask layer and exposes a portion of a surface of the semiconductor substrate. Then, a first semiconductor pattern is formed in the first opening. Then, a second mask layer is formed over the first semiconductor pattern and the first mask layer. Then, at least a second opening is formed through the second mask layer to the first mask layer and exposes another portion of the surface of the semiconductor substrate. And, a second semiconductor pattern is formed in the second opening.
    Type: Application
    Filed: August 15, 2013
    Publication date: February 19, 2015
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: Hung-Lin Shih, Chih-Chien Liu, Jei-Ming Chen, Wen-Yi Teng, Chieh-Wen Lo