Patents by Inventor Chieh-Wen Shih

Chieh-Wen Shih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220188673
    Abstract: A mixed-precision artificial intelligence (AI) processor and an operating method thereof are provided. The AI processor includes a first calculation module, a second calculation module and a control module. The first calculation module is configured to perform calculation based on the data with a first format. The second calculation module is configured to perform calculation based on the data with a second format different from the first format. The control module is coupled to the first calculation module and the second calculation module to select one of the first calculation module or the second calculation module to perform calculation based on an input data according to a calculation strategy.
    Type: Application
    Filed: December 14, 2021
    Publication date: June 16, 2022
    Inventors: Chia-Lin LU, Yuan-Hsiang KUO, Wei-Chun CHANG, Jen-Shi WU, Chieh-Wen SHIH
  • Patent number: 8850248
    Abstract: A multi-core electronic system for accessing a data storage device includes a plurality of processors, a data transmission interface and a rate adjustment module. The processors respectively provide a bandwidth requirement, and communicate with the data storage device via the shared data transmission interface. The rate adjustment module receives the bandwidth requirements, and determines a transmission rate of the data transmission interface according to the bandwidth requirements.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: September 30, 2014
    Assignee: MStar Semiconductor, Inc.
    Inventors: Ping-Cheng Hou, Cheng-Yu Lu, Chieh-Wen Shih, Jen-Shi Wu, Chung-Ching Chen
  • Publication number: 20120272080
    Abstract: A multi-core electronic system for accessing a data storage device includes a plurality of processors, a data transmission interface and a rate adjustment module. The processors respectively provide a bandwidth requirement, and communicate with the data storage device via the shared data transmission interface. The rate adjustment module receives the bandwidth requirements, and determines a transmission rate of the data transmission interface according to the bandwidth requirements.
    Type: Application
    Filed: July 26, 2011
    Publication date: October 25, 2012
    Applicant: MSTAR SEMICONDUCTOR, INC.
    Inventors: Ping-Cheng Hou, Cheng-Yu Lu, Chieh-Wen Shih, Jen-Shi Wu, Chung-Ching Chen
  • Patent number: 7886117
    Abstract: A method of memory management is disclosed. The invention increases bank diversity by splitting requests and is also integrated with re-ordering and priority arbitration mechanisms. Therefore, the probabilities of both bank conflicts and write-to-read turnaround conflicts are reduced significantly, so as to increase memory efficiency.
    Type: Grant
    Filed: September 20, 2007
    Date of Patent: February 8, 2011
    Assignee: Realtalk Semiconductor Corp.
    Inventor: Chieh-Wen Shih
  • Publication number: 20080104340
    Abstract: A method of memory management is disclosed. The invention increases bank diversity by splitting requests and is also integrated with re-ordering and priority arbitration mechanisms. Therefore, the probabilities of both bank conflicts and write-to-read turnaround conflicts are reduced significantly, so as to increase memory efficiency.
    Type: Application
    Filed: September 20, 2007
    Publication date: May 1, 2008
    Applicant: REALTEK SEMICONDUCTOR CORP.
    Inventor: Chieh-Wen Shih