Abstract: A photoresist includes a solvent, a polymer and an additive. The polymer is dissolved in the solvent, and the additive is dispersed in the solvent. The additive includes a double bond or includes an epoxy group. The additive has a surface tension different from a surface tension of the polymer.

Abstract: A method of manufacturing a semiconductor device includes forming a first layer comprising an organic material over a substrate. A second layer is formed over the first layer, wherein the second layer includes a silicon-containing material and one or more selected from the group consisting of a photoacid generator, an actinic radiation absorbing additive including an iodine substituent, and a silicon-containing monomer having iodine or phenol group substituents. A photosensitive layer is formed over the second layer, and the photosensitive layer is patterned.

Abstract: A photoresist includes a polymer and a photoactive compound. The photoactive compound contains a sensitizer component. The photoactive compound contains an acid generator or a base molecular. The acid generator or the base molecular bonds the sensitizer component. The photoactive compound is within a polymer backbone. The sensitizer component is configured to absorb an EUV light to produce electrons.

Abstract: Certain aspects provide a circuit for analog-to-digital conversion. The circuit generally includes a flash analog-to-digital converter (ADC) having a plurality of comparators, each comparator being configured to compare an input voltage to a reference voltage; and a calibration circuit coupled to the flash ADC and configured to tune the reference voltage prior to a conversion operation by the flash ADC.

Abstract: Multi-channel receiver circuits implemented with time-multiplexed successive approximation register (SAR) analog-to-digital converter (ADC) circuits and methods for operating such receiver circuits are disclosed. One example receiver circuit generally includes a first multiplexer having a plurality of inputs coupled to a plurality of in-phase (I) receive paths associated with different channels of the receiver circuit, a first SAR ADC circuit having an input coupled to an output of the first multiplexer, a second multiplexer having a plurality of inputs coupled to a plurality of quadrature (Q) receive paths associated with the different channels of the receiver circuit, and a second SAR ADC circuit having an input coupled to an output of the second multiplexer.

Abstract: A method and an apparatus for splitting a switched capacitor integrator of a delta-sigma modulator are provided. The apparatus configures a first integrator and a second integrator to be coupled in parallel to each other, switches between a first mode and a second mode, enables the first integrator to operate on an input signal to generate an output signal in the first mode, and enables the first integrator and the second integrator to cooperatively operate on the input signal in the second mode, wherein in the second mode, the apparatus generates a first output via the first integrator, generates a second output via the second integrator, and converges the first output with the second output to generate the output signal.

Abstract: A method and an apparatus for splitting a switched capacitor integrator of a delta-sigma modulator are provided. The apparatus configures a first integrator and a second integrator to be coupled in parallel to each other, switches between a first mode and a second mode, enables the first integrator to operate on an input signal to generate an output signal in the first mode, and enables the first integrator and the second integrator to cooperatively operate on the input signal in the second mode, wherein in the second mode, the apparatus generates a first output via the first integrator, generates a second output via the second integrator, and converges the first output with the second output to generate the output signal.

Abstract: An analog-to-digital converter (ADC) and a receiver that includes the ADC is disclosed. The ADC includes a first filter configured to receive a signal in an I-signal path of the receiver and a second filter configured to receive a signal in a Q-signal path of the receiver. The ADC further includes a quantizer alternatingly in connection with the first and second filters, and at least one DAC alternatingly in connection with the first and second filters. Switches in the ADC are configured to alternate connection between an input of the quantizer and outputs of the first and second filters, and are also configured to alternate connection between an output of the at least one DAC and inputs of the first and second filters.

Abstract: An analog-to-digital converter (ADC) and a receiver that includes the ADC is disclosed. The ADC includes a first filter configured to receive a signal in an I-signal path of the receiver and a second filter configured to receive a signal in a Q-signal path of the receiver. The ADC further includes a quantizer alternatingly in connection with the first and second filters, and at least one DAC alternatingly in connection with the first and second filters. Switches in the ADC are configured to alternate connection between an input of the quantizer and outputs of the first and second filters, and are also configured to alternate connection between an output of the at least one DAC and inputs of the first and second filters.