Patents by Inventor Chieh-Yu Lin
Chieh-Yu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240054050Abstract: Error correcting memory systems and methods of operating the memory systems are disclosed. In some embodiments, a memory system includes: a data memory; an ECC memory; and a data scrubbing circuit electrically coupled to the ECC memory and the data memory. The data scrubbing circuit may be configured to, in response to receiving a scrub data command, correct an error in the data memory. A code word length used to correct the error may be longer than a word length used during normal access of the data memory. In some embodiments, a memory system includes a first memory circuit associated with a first bit error rate and a second memory circuit associated with a second bit error rate. In some embodiments, a memory system includes an error correctable multi-level cell (MLC) array.Type: ApplicationFiled: July 17, 2023Publication date: February 15, 2024Applicant: SuperMem, Inc.Inventors: Yu LU, Chieh-yu LIN
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Publication number: 20230320329Abstract: A poultry voiceprint identification system includes a receiver, a feature processing module, a feature analysis module and an artificial intelligence sound model. The receiver is arranged in a poultry house for receiving a recording information of a poultry house for a period of time. A stocking density of poultry in the poultry house is 7 per square meter or more. The feature processing module converts the recording information into a plurality of sound features via filtering, segmentation and extraction methods. The artificial intelligence sound model generates a training group according to the sound features. The feature analysis module analyzes each sound feature to determine a sound state of each sound feature through an artificial intelligence sound model. The sound state includes a normal poultry sound state or an abnormal poultry sound state. The system accurately and quickly identifies the sound from abnormal poultry among high stocking density poultry.Type: ApplicationFiled: April 10, 2023Publication date: October 12, 2023Applicant: iChase Co., Ltd.Inventors: Chieh-yu LIN, Kuang-fu CHANG, Li-wan HUANG
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Patent number: 11748194Abstract: Error correcting memory systems and methods of operating the memory systems are disclosed. In some embodiments, a memory system includes: a data memory; an ECC memory; and a data scrubbing circuit electrically coupled to the ECC memory and the data memory. The data scrubbing circuit may be configured to, in response to receiving a scrub data command, correct an error in the data memory. A code word length used to correct the error may be longer than a word length used during normal access of the data memory. In some embodiments, a memory system includes a first memory circuit associated with a first bit error rate and a second memory circuit associated with a second bit error rate. In some embodiments, a memory system includes an error correctable multi-level cell (MLC) array.Type: GrantFiled: December 17, 2021Date of Patent: September 5, 2023Assignee: SuperMem, Inc.Inventors: Yu Lu, Chieh-yu Lin
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Publication number: 20220399060Abstract: Memories, memory controllers, and computing systems and their methods of operation are disclosed. In some embodiments, a method of accessing a memory includes accessing a first bit line corresponding to a sense amplifier and accessing a second bit line corresponding to the sense amplifier. In some embodiments, a memory controller includes a second memory configured to store data of a second data type. In some embodiments, a method includes operating a memory in a second mode in response to receiving an input to change the operation of the memory from a first mode to the second mode.Type: ApplicationFiled: August 14, 2020Publication date: December 15, 2022Applicant: SuperMem, Inc.Inventors: Yu LU, Chieh-yu LIN
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Publication number: 20220188187Abstract: Error correcting memory systems and methods of operating the memory systems are disclosed. In some embodiments, a memory system includes: a data memory; an ECC memory; and a data scrubbing circuit electrically coupled to the ECC memory and the data memory. The data scrubbing circuit may be configured to, in response to receiving a scrub data command, correct an error in the data memory. A code word length used to correct the error may be longer than a word length used during normal access of the data memory. In some embodiments, a memory system includes a first memory circuit associated with a first bit error rate and a second memory circuit associated with a second bit error rate. In some embodiments, a memory system includes an error correctable multi-level cell (MLC) array.Type: ApplicationFiled: December 17, 2021Publication date: June 16, 2022Applicant: SuperMem, Inc.Inventors: Yu LU, Chieh-yu LIN
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Patent number: 11204835Abstract: Error correcting memory systems and methods of operating the memory systems are disclosed. In some embodiments, a memory system includes: a data memory; an ECC memory; and a data scrubbing circuit electrically coupled to the ECC memory and the data memory. The data scrubbing circuit may be configured to, in response to receiving a scrub data command, correct an error in the data memory. A code word length used to correct the error may be longer than a word length used during normal access of the data memory. In some embodiments, a memory system includes a first memory circuit associated with a first bit error rate and a second memory circuit associated with a second bit error rate. In some embodiments, a memory system includes an error correctable multi-level cell (MLC) array.Type: GrantFiled: October 11, 2019Date of Patent: December 21, 2021Assignee: SuperMem, Inc.Inventors: Yu Lu, Chieh-yu Lin
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Patent number: 11191488Abstract: Example apparatus are provided to measure characteristics of a test strip. The apparatus may include an accessory for a mobile device to measure characteristics of a test strip. The accessory may include a mobile device adaptor and a test strip adaptor. The mobile device adaptor may include a first sheath and a second sheath coupled to the first sheath to secure the mobile device. The test strip adaptor may be detachably coupled to the mobile device adapter. The test strip adaptor is configured to receive different types of test strips.Type: GrantFiled: March 16, 2018Date of Patent: December 7, 2021Inventors: Yenyu Chen, Yao Ching Tsai, Jheng Long Jiang, Chieh Yu Lin, Chun Hun Shen
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Publication number: 20210311827Abstract: Error correcting memory systems and methods of operating the memory systems are disclosed. In some embodiments, a memory system includes: a data memory; an ECC memory; and a data scrubbing circuit electrically coupled to the ECC memory and the data memory. The data scrubbing circuit may be configured to, in response to receiving a scrub data command, correct an error in the data memory. A code word length used to correct the error may be longer than a word length used during normal access of the data memory. In some embodiments, a memory system includes a first memory circuit associated with a first bit error rate and a second memory circuit associated with a second bit error rate. In some embodiments, a memory system includes an error correctable multi-level cell (MLC) array.Type: ApplicationFiled: October 11, 2019Publication date: October 7, 2021Applicant: SuperMem, Inc.Inventors: Yu LU, Chieh-yu LIN
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Patent number: 11036126Abstract: Technical solutions are described for fabricating a semiconductor wafer. An example method includes generating a process assumption band for an element of the wafer. The process assumption band depicts a shape of the element based on a set of process variations in a photolithographic process used for fabricating the wafer. The method also includes generating a process variation band for the element of the wafer based on optical process correction simulation of the photolithographic process using design rules associated with the wafer. The method also includes determining a deviation between the process assumption band and the process variation band, and recalculating one or more design rules from the design rules associated with the wafer based on the deviation. The method also includes updating the design of the wafer in response to the process variation band not being changeable to match the process assumption band, after recalculating the design rules.Type: GrantFiled: June 14, 2019Date of Patent: June 15, 2021Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chieh-Yu Lin, Dongbing Shao, Kehan Tian, Zheng Xu
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Publication number: 20200375543Abstract: Example apparatus are provided to measure characteristics of a test strip. The apparatus may include an accessory for a mobile device to measure characteristics of a test strip. The accessory may include a mobile device adaptor and a test strip adaptor. The mobile device adaptor may include a first sheath and a second sheath coupled to the first sheath to secure the mobile device. The test strip adaptor may be detachably coupled to the mobile device adapter. The test strip adaptor is configured to receive different types of test strips.Type: ApplicationFiled: March 16, 2018Publication date: December 3, 2020Applicant: iXensor CO., LTD.Inventors: Yenyu CHEN, Yao Ching TSAI, Jheng Long JIANG, Chieh Yu LIN, Chun Hun SHEN
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Patent number: 10585346Abstract: Technical solutions are described for fabricating a semiconductor wafer. An example method includes generating a process assumption band for an element of the wafer. The process assumption band depicts a shape of the element based on a set of process variations in a photolithographic process used for fabricating the wafer. The method also includes generating a process variation band for the element of the wafer based on optical process correction simulation of the photolithographic process using design rules associated with the wafer. The method also includes determining a deviation between the process assumption band and the process variation band, and recalculating one or more design rules from the design rules associated with the wafer based on the deviation. The method also includes updating the design of the wafer in response to the process variation band not being changeable to match the process assumption band, after recalculating the design rules.Type: GrantFiled: November 21, 2017Date of Patent: March 10, 2020Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC.Inventors: Chieh-Yu Lin, Dongbing Shao, Kehan Tian, Zheng Xu
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Publication number: 20190294039Abstract: Technical solutions are described for fabricating a semiconductor wafer. An example method includes generating a process assumption band for an element of the wafer. The process assumption band depicts a shape of the element based on a set of process variations in a photolithographic process used for fabricating the wafer. The method also includes generating a process variation band for the element of the wafer based on optical process correction simulation of the photolithographic process using design rules associated with the wafer. The method also includes determining a deviation between the process assumption band and the process variation band, and recalculating one or more design rules from the design rules associated with the wafer based on the deviation. The method also includes updating the design of the wafer in response to the process variation band not being changeable to match the process assumption band, after recalculating the design rules.Type: ApplicationFiled: June 14, 2019Publication date: September 26, 2019Inventors: CHIEH-YU LIN, DONGBING SHAO, KEHAN TIAN, ZHENG XU
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Patent number: 10394116Abstract: Technical solutions are described for fabricating a semiconductor wafer. An example method includes generating a process assumption band for an element of the wafer. The process assumption band depicts a shape of the element based on a set of process variations in a photolithographic process used for fabricating the wafer. The method also includes generating a process variation band for the element of the wafer based on optical process correction simulation of the photolithographic process using design rules associated with the wafer. The method also includes determining a deviation between the process assumption band and the process variation band, and recalculating one or more design rules from the design rules associated with the wafer based on the deviation. The method also includes updating the design of the wafer in response to the process variation band not being changeable to match the process assumption band, after recalculating the design rules.Type: GrantFiled: September 6, 2017Date of Patent: August 27, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chieh-Yu Lin, Dongbing Shao, Kehan Tian, Zheng Xu
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Publication number: 20190072845Abstract: Technical solutions are described for fabricating a semiconductor wafer. An example method includes generating a process assumption band for an element of the wafer. The process assumption band depicts a shape of the element based on a set of process variations in a photolithographic process used for fabricating the wafer. The method also includes generating a process variation band for the element of the wafer based on optical process correction simulation of the photolithographic process using design rules associated with the wafer. The method also includes determining a deviation between the process assumption band and the process variation band, and recalculating one or more design rules from the design rules associated with the wafer based on the deviation. The method also includes updating the design of the wafer in response to the process variation band not being changeable to match the process assumption band, after recalculating the design rules.Type: ApplicationFiled: September 6, 2017Publication date: March 7, 2019Inventors: CHIEH-YU LIN, DONGBING SHAO, KEHAN TIAN, ZHENG XU
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Publication number: 20190072846Abstract: Technical solutions are described for fabricating a semiconductor wafer. An example method includes generating a process assumption band for an element of the wafer. The process assumption band depicts a shape of the element based on a set of process variations in a photolithographic process used for fabricating the wafer. The method also includes generating a process variation band for the element of the wafer based on optical process correction simulation of the photolithographic process using design rules associated with the wafer. The method also includes determining a deviation between the process assumption band and the process variation band, and recalculating one or more design rules from the design rules associated with the wafer based on the deviation. The method also includes updating the design of the wafer in response to the process variation band not being changeable to match the process assumption band, after recalculating the design rules.Type: ApplicationFiled: November 21, 2017Publication date: March 7, 2019Inventors: CHIEH-YU LIN, DONGBING SHAO, KEHAN TIAN, ZHENG XU
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Patent number: 10032794Abstract: A semiconductor device includes a plurality of gates formed upon a semiconductor substrate that includes a plurality of outer active areas (e.g. CMOS/PMOS areas, source/drain regions, etc.) and one or more inner active areas. An isolator is formed upon one or more inner gates associated with the one or more inner active areas. A contact bar electrically connects the outer active areas and/or outer gates and is formed upon the isolator. The isolator electrically insulates the contact bar from the one or more inner active areas and/or the one or more inner gates.Type: GrantFiled: October 27, 2017Date of Patent: July 24, 2018Assignees: International Business Machines Corporation, STMicroelectronics, Inc.Inventors: Wai-Kin Li, Chieh-Yu Lin, Yannick Daurelle
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Rule and process assumption co-optimization using feature-specific layout-based statistical analyses
Patent number: 9898573Abstract: Disclosed are methods, systems and computer program products that, during new technology node development, perform design rule and process assumption co-optimization using feature-specific layout-based statistical analyses. Specifically, the layout of a given feature can be analyzed to determine whether it complies with all of the currently established design rules in the new technology node. When the layout fails to comply with a current design rule, statistical analyses (e.g., Monte-Carlo simulations) of images, which are generated based on the layout and which illustrate different tolerances for and between the various shapes in the layout given current process assumption(s), can be performed. Based on the results of the analyses, the current process assumption(s) and/or the design rule itself can be adjusted using a co-optimization process in order to ensure the manufacturability of the feature within the technology.Type: GrantFiled: February 10, 2016Date of Patent: February 20, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: James A. Culp, Chieh-Yu Lin, Dongbing Shao -
Publication number: 20180047755Abstract: A semiconductor device includes a plurality of gates formed upon a semiconductor substrate that includes a plurality of outer active areas (e.g. CMOS/PMOS areas, source/drain regions, etc.) and one or more inner active areas. An isolator is formed upon one or more inner gates associated with the one or more inner active areas. A contact bar electrically connects the outer active areas and/or outer gates and is formed upon the isolator. The isolator electrically insulates the contact bar from the one or more inner active areas and/or the one or more inner gates.Type: ApplicationFiled: October 27, 2017Publication date: February 15, 2018Inventors: Wai-Kin Li, Chieh-Yu Lin, Yannick Daurelle
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Patent number: 9859303Abstract: A semiconductor device includes a plurality of gates formed upon a semiconductor substrate that includes a plurality of outer active areas (e.g. CMOS/PMOS areas, source/drain regions, etc.) and one or more inner active areas. An isolator is formed upon one or more inner gates associated with the one or more inner active areas. A contact bar electrically connects the outer active areas and/or outer gates and is formed upon the isolator. The isolator electrically insulates the contact bar from the one or more inner active areas and/or the one or more inner gates.Type: GrantFiled: September 23, 2016Date of Patent: January 2, 2018Assignees: International Business Machines Corporation, STMicroelectronics, Inc.Inventors: Wai-Kin Li, Chieh-Yu Lin, Yannick Daurelle
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Patent number: D902304Type: GrantFiled: October 15, 2018Date of Patent: November 17, 2020Inventors: Jonathan Perry, Chieh-Yu Lin