Patents by Inventor Chieko Nakashima
Chieko Nakashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8576608Abstract: A memory apparatus includes: a plurality of memory cells which includes a first resistance change element; and a read-out circuit which determines the size of a resistance value of the first resistance change element by comparing the resistance state of a memory cell selected among the plurality of memory cells to the resistance state of a reference memory cell, wherein the reference memory cell includes a second resistance change element, a resistance value of the second resistance change element with respect to an applied voltage is smaller than that in a high resistance state of the first resistance change element, and the second resistance change element shows the same resistance change characteristic as the first resistance change element.Type: GrantFiled: December 5, 2011Date of Patent: November 5, 2013Assignee: Sony CorporationInventors: Tomohito Tsushima, Makoto Kitagawa, Tsunenori Shiimoto, Chieko Nakashima, Hiroshi Yoshihara, Kentaro Ogata
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Publication number: 20120212994Abstract: A memory apparatus includes: a plurality of memory cells which includes a first resistance change element; and a read-out circuit which determines the size of a resistance value of the first resistance change element by comparing the resistance state of a memory cell selected among the plurality of memory cells to the resistance state of a reference memory cell, wherein the reference memory cell includes a second resistance change element, a resistance value of the second resistance change element with respect to an applied voltage is smaller than that in a high resistance state of the first resistance change element, and the second resistance change element shows the same resistance change characteristic as the first resistance change element.Type: ApplicationFiled: December 5, 2011Publication date: August 23, 2012Applicant: Sony CorporationInventors: Tomohito Tsushima, Makoto Kitagawa, Tsunenori Shiimoto, Chieko Nakashima, Hiroshi Yoshihara, Kentaro Ogata
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Publication number: 20110222355Abstract: Disclosed herein is a control voltage generation circuit including: a reference voltage generation circuit adapted to generate a reference voltage; and a voltage conversion circuit adapted to generate, based on the reference voltage, a control voltage to be supplied to the gate of a clamping transistor connected between a bit line and a sense amplifier to adjust the voltage of the bit line, wherein the voltage conversion circuit outputs a voltage, which is the sum of a voltage proportional to the reference voltage and a voltage equivalent to the threshold voltage of the clamping transistor, to the gate of the clamping transistor as the control voltage.Type: ApplicationFiled: March 2, 2011Publication date: September 15, 2011Applicant: Sony CorporationInventors: Chieko Nakashima, Tomohiro Namise, Tsunenori Shiimoto
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Patent number: 7471543Abstract: A storage device includes a memory cell having a storage element having a characteristic of changing from a state of a high resistance value to a state of a low resistance value by being supplied with a voltage equal to or higher than a first threshold voltage, and changing from a state of a low resistance value to a state of a high resistance value by being supplied with a voltage equal to or higher than a second threshold voltage different in polarity from the first threshold voltage, and a circuit element connected in series with the storage element, wherein letting R be a resistance value of the storage element after writing, V be the second threshold voltage, and I be a current that can be passed through the storage element at a time of erasure, R?V/I.Type: GrantFiled: September 11, 2006Date of Patent: December 30, 2008Assignee: Sony CorporationInventors: Chieko Nakashima, Hidenari Hachino, Hajime Nagao, Nobumichi Okazaki
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Patent number: 7372718Abstract: A storage device includes a storage element having characteristics such that the resistance value thereof changes from a high state to a low state as a result of an electrical signal higher than or equal to a first threshold signal being applied and changes from a low state to a high state as a result of an electrical signal higher than or equal to a second threshold signal whose polarity differs from that of the first threshold signal being applied; and a circuit element that is connected in series to the storage element and that serves as a load, the storage element and the circuit element forming a memory cell, and the memory cells being arranged in a matrix, wherein the resistance value of the circuit element when the storage element is read differs from the resistance value when the storage element is written or erased.Type: GrantFiled: October 4, 2005Date of Patent: May 13, 2008Assignee: Sony CorporationInventors: Hajime Nagao, Hidenari Hachino, Tsutomu Sagara, Hironobu Mori, Nobumichi Okazaki, Wataru Ootsuka, Tomohito Tsushima, Chieko Nakashima
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Patent number: 7242606Abstract: A storage apparatus includes memory devices each having a storage element with a characteristic that the application of an electric signal not lower than a first threshold signal allows the storage element to shift from a high resistance value state to a low resistance value state, and that the application of an electric signal not lower than a second threshold signal, which has a polarity different from that of the first threshold signal, allows the storage element to shift form a low resistance value state to a high resistance value state, and a circuit element connected to the storage element in series to be a load; wherein the memory devices are arranged in a matrix and one terminal of each of the memory devices is connected to a common line; and wherein an intermediate potential between a power supply potential and a ground potential is applied to the common line.Type: GrantFiled: September 13, 2005Date of Patent: July 10, 2007Assignee: Sony CorporationInventors: Hidenari Hachino, Nobumichi Okazaki, Wataru Otsuka, Tomohito Tsushima, Tsutomu Sagara, Chieko Nakashima, Hironobu Mori, Hajime Nagao
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Patent number: 7209379Abstract: A storage device is proposed, which includes: a source line arranged along a row direction; a bit line arranged along a column direction; a storage element arranged at an intersection of the source line and the bit line; a writing circuit connected to one terminal of the bit line and applying a predetermined voltage to the bit line; and a voltage adjusting circuit connected to a storage element that is located closest to another terminal of the bit line; wherein the voltage adjusting circuit compares the voltage applied to the storage element located closest to the another terminal of the bit line with a setting voltage to thereby adjust the voltage that the writing circuit applies to the bit line.Type: GrantFiled: September 13, 2005Date of Patent: April 24, 2007Assignee: Sony CorporationInventors: Hironobu Mori, Hidenari Hachino, Chieko Nakashima, Tsutomu Sagara, Nobumichi Okazaki, Hajime Nagao
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Publication number: 20070070682Abstract: A storage device includes a memory cell having a storage element having a characteristic of changing from a state of a high resistance value to a state of a low resistance value by being supplied with a voltage equal to or higher than a first threshold voltage, and changing from a state of a low resistance value to a state of a high resistance value by being supplied with a voltage equal to or higher than a second threshold voltage different in polarity from the first threshold voltage, and a circuit element connected in series with the storage element, wherein letting R be a resistance value of the storage element after writing, V be the second threshold voltage, and I be a current that can be passed through the storage element at a time of erasure, R?V/I.Type: ApplicationFiled: September 11, 2006Publication date: March 29, 2007Inventors: Chieko Nakashima, Hidenari Hachino, Hajime Nagao, Nobumichi Okazaki
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Publication number: 20060109316Abstract: A storage device includes a storage element having characteristics such that the resistance value thereof changes from a high state to a low state as a result of an electrical signal higher than or equal to a first threshold signal being applied and changes from a low state to a high state as a result of an electrical signal higher than or equal to a second threshold signal whose polarity differs from that of the first threshold signal being applied; and a circuit element that is connected in series to the storage element and that serves as a load, the storage element and the circuit element forming a memory cell, and the memory cells being arranged in a matrix, wherein the resistance value of the circuit element when the storage element is read differs from the resistance value when the storage element is written or erased.Type: ApplicationFiled: October 4, 2005Publication date: May 25, 2006Inventors: Hajime Nagao, Hidenari Hachino, Tsutomu Sagara, Hironobu Mori, Nobumichi Okazaki, Wataru Ootsuka, Tomohito Tsushima, Chieko Nakashima
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Publication number: 20060067114Abstract: A storage apparatus includes memory devices each having a storage element with a characteristic that the application of an electric signal not lower than a first threshold signal allows the storage element to shift from a high resistance value state to a low resistance value state, and that the application of an electric signal not lower than a second threshold signal, which has a polarity different from that of the first threshold signal, allows the storage element to shift form a low resistance value state to a high resistance value state, and a circuit element connected to the storage element in series to be a load; wherein the memory devices are arranged in a matrix and one terminal of each of the memory devices is connected to a common line; and wherein an intermediate potential between a power supply potential and a ground potential is applied to the common line.Type: ApplicationFiled: September 13, 2005Publication date: March 30, 2006Inventors: Hidenari Hachino, Nobumichi Okazaki, Wataru Otsuka, Tomohito Tsushima, Tsutomu Sagara, Chieko Nakashima, Hironobu Mori, Hajime Nagao
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Publication number: 20060067106Abstract: A storage device is proposed, which includes: a source line arranged along a row direction; a bit line arranged along a column direction; a storage element arranged at an intersection of the source line and the bit line; a writing circuit connected to one terminal of the bit line and applying a predetermined voltage to the bit line; and a voltage adjusting circuit connected to a storage element that is located closest to another terminal of the bit line; wherein the voltage adjusting circuit compares the voltage applied to the storage element located closest to the another terminal of the bit line with a setting voltage to thereby adjust the voltage that the writing circuit applies to the bit line.Type: ApplicationFiled: September 13, 2005Publication date: March 30, 2006Inventors: Hironobu Mori, Hidenari Hachino, Chieko Nakashima, Tsutomu Sagara, Nobumichi Okazaki, Hajime Nagao