Abstract: Semiconductor dies of a semiconductor die package are directly bonded, and a top metal region may be formed over the semiconductor dies. A plurality of conductive terminals may be formed over the top metal region. The conductive terminals are formed of copper (Cu) or another material that enables low-temperature deposition process techniques, such as electroplating, to be used to form the conductive terminal. In this way, the conductive terminals of the semiconductor die packages described herein may be formed at a relatively low temperature. This reduces the likelihood of thermal deformation of semiconductor dies in the semiconductor die packages. The reduced thermal deformation reduces the likelihood of warpage, breakage, and/or other types of damage to the semiconductor dies of the semiconductor die packages, which may increase performance and/or increase yield of semiconductor die packages.

Abstract: A layer stack including a first bonding dielectric material layer, a dielectric metal oxide layer, and a second bonding dielectric material layer is formed over a top surface of a substrate including a substrate semiconductor layer. A conductive material layer is formed by depositing a conductive material over the second bonding dielectric material layer. The substrate semiconductor layer is thinned by removing portions of the substrate semiconductor layer that are distal from the layer stack, whereby a remaining portion of the substrate semiconductor layer includes a top semiconductor layer. A semiconductor device may be formed on the top semiconductor layer.

Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.

Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, and a buffer layer. The first die and the second die are disposed side by side. The first encapsulant encapsulates the first die and the second die. The second die includes a die stack encapsulated by a second encapsulant encapsulating a die stack. The buffer layer is disposed between the first encapsulant and the second encapsulant and covers at least a sidewall of the second die and disposed between the first encapsulant and the second encapsulant. The buffer layer has a Young's modulus less than a Young's modulus of the first encapsulant and a Young's modulus of the second encapsulant.

Abstract: A device includes a bottom transistor, a top transistor, and an epitaxial isolation structure. The bottom transistor includes a first channel layer, first source/drain epitaxial structures, and a first gate structure. The first source/drain epitaxial structures are on opposite sides of the first channel layer. The first gate structure is around the first channel layer. The top transistor is over the bottom transistor and includes a second channel layer, second source/drain epitaxial structures, and a second gate structure. The second source/drain epitaxial structures are on opposite sides of the second channel layer. The second gate structure is around the second channel layer. The epitaxial isolation structure is between and in contact with one of the first source/drain epitaxial structures and one of the second source/drain epitaxial structures, such that the one of the first source/drain epitaxial structures is electrically isolated from the one of the second source/drain epitaxial structures.

Abstract: A memory device and a management method thereof are provided. The memory device includes a controller and at least one memory channel. The memory channel includes at least one memory chip. The at least one memory chip is commonly coupled to the controller through an interrupt signal wire. The at least one memory chip generates at least one local interrupt signal and performs a logic operation on the at least one local interrupt signal to generate a common interrupt signal. The interrupt signal wire is configured to transmit the common interrupt signal to the controller.

Abstract: A semiconductor device according to embodiments of the present disclosure includes a first die including a first bonding layer and a second die including a second hybrid bonding layer. The first bonding layer includes a first dielectric layer and a first metal coil embedded in the first dielectric layer. The second bonding layer includes a second dielectric layer and a second metal coil embedded in the second dielectric layer. The second hybrid bonding layer is bonded to the first hybrid bonding layer such that the first dielectric layer is bonded to the second dielectric layer and the first metal coil is bonded to the second metal coil.

Abstract: To prevent arcing discharge of a liquid crystal device. Provided is a liquid crystal device including a liquid crystal layer, a first substrate, a second substrate and an insulating film, wherein the liquid crystal layer is arranged between the first substrate and the second substrate, the first substrate includes electrode 1, the second substrate includes electrode 2, the insulating film is arranged between electrode 1 and electrode 2, and the insulating film is a cured product of a thermosetting polymer composition.

Abstract: The disclosed may include various systems and methods for improving the efficiency and scalability of large-scale systems. For example, the disclosed may include systems and methods for automatic privacy enforcement using privacy-aware infrastructure, scalable general-purpose low cost integer motion search, efficient scaler filter coefficients layout for flexible scaling quality control with limited hardware resources, hardware optimization for power saving with both different codecs enabled, optimizing storage overhead and performance for large distributed data warehouse, mass and volume efficient integration of intersatellite link terminals to a satellite bus, and overcoming retention limit for memory-based distributed database systems.

Abstract: A method for compensating voltage drop with additional power mesh and a circuit system thereof are provided. In the method, circuit layout of the system is segmented into one or more regions. A layout overflow analysis is performed on each of the regions. A routing overflow rate for each region is calculated according to a ratio of an area occupied by signal tracks and power tracks of a power mesh to another area provided for whole route tracks in the same region. After considering a ranking of the routing overflow rates of the regions, the widths of metal wires, a predetermined ratio of IR drop compensation for the circuit system, and a degree of electron migration to be improved, the additional power tracks of the power mesh deployed to the circuit system are decided. The additional power tracks of the power mesh can effectively improve the IR drop.

Abstract: The application discloses a semiconductor device and a semiconductor device manufacturing method. The semiconductor device includes: a substrate; a circuit macro on the substrate; a plurality of metal layers over the substrate, wherein the plurality of metal layers include a first power mesh; and a plurality of power switch circuits on the substrate, wherein the power switch circuits selectively couple a power to the first power mesh according to a control signal, and the power switch circuits are arranged in sequence, wherein a control signal output terminal of each first power switch circuit is coupled to a control signal input terminal of a following first power switch circuit, so that the control signal passes through the first power switch circuits sequentially.

Abstract: A method for performing power mesh optimization with the aid of additional wires and an associated apparatus are provided. The method includes: reading a clock cell definition file to obtain respective basic information of a plurality of clock cells in a circuit design; and according to the respective basic information of the plurality of clock cells, executing a power mesh optimization procedure, including: regarding any type of clock cells in multiple types of clock cells within the plurality of clock cells, classifying the clock cells into a plurality of sub-types according to respective sizes of the type of clock cells; and performing power mesh enhancement on respective clock cells of a set of sub-types within the plurality of sub-types, to add a set of additional wires crossing a set of original wires in an original power mesh at each clock cell of any sub-type of the set of sub-types.

Abstract: A method for performing power mesh optimization with the aid of additional wires and an associated apparatus are provided. The method includes: reading a clock cell definition file to obtain respective basic information of a plurality of clock cells in a circuit design; and according to the respective basic information of the plurality of clock cells, executing a power mesh optimization procedure, including: regarding any type of clock cells in multiple types of clock cells within the plurality of clock cells, classifying the clock cells into a plurality of sub-types according to respective sizes of the type of clock cells; and performing power mesh enhancement on respective clock cells of a set of sub-types within the plurality of sub-types, to add a set of additional wires crossing a set of original wires in an original power mesh at each clock cell of any sub-type of the set of sub-types.

Abstract: A method of using a simulation software to generate a circuit layout, the method comprising: (A) determining a plurality of blocks on a circuit board, wherein each block of the plurality of blocks includes an operating space and a reserved space; (B) determining a size of the reserved space of each block of the plurality of blocks according to at least one specific condition;(C) determining whether to adjust the size of the reserved space of each block of the plurality of blocks according to at least one determining condition; and (D) when it is determined not to adjust the size of the reserved space in step (C), generating the circuit layout according to the size of the reserved space of each block of the plurality of blocks determined in step (B).

Abstract: A method of using simulation software to generate circuit layout includes: (A) determining a plurality of blocks on a circuit board, wherein each block includes an operating space and a reserved space; (B) determining a size of the reserved space of each of the blocks according to at least one specific condition; (C) determining whether to adjust the size of the reserved space of the blocks according to at least one determining condition; and (D) when it is determined not to adjust the size of the reserved space in step (C), generating the circuit layout according to the size of the reserved space of the blocks determined in step (B).

Abstract: A circuit structure is electrically connected to a power source. The circuit structure includes a first circuit module and a second circuit module. The first circuit module includes a first module power switch and a plurality of circuits. The first module power switch is electrically connected to the power source. The first circuit module has a first module current. The second circuit module includes a second module power switch and a plurality of circuits. The second power switch is electrically connected to the power source. The second circuit module has a second module current. A turn-on order of the first module power switch and the second power switch is determined based on the first module current and the second module current.

Abstract: A circuit structure is electrically connected to a power source. The circuit structure includes a first circuit module and a second circuit module. The first circuit module includes a first module power switch and a plurality of circuits. The first module power switch is electrically connected to the power source. The first circuit module has a first module current. The second circuit module includes a second module power switch and a plurality of circuits. The second power switch is electrically connected to the power source. The second circuit module has a second module current. A turn-on order of the first module power switch and the second power switch is determined based on the first module current and the second module current.

Abstract: To prevent arcing discharge of a liquid crystal device. Provided is a liquid crystal device including a liquid crystal layer, a first substrate, a second substrate and an insulating film, wherein the liquid crystal layer is arranged between the first substrate and the second substrate, the first substrate includes electrode 1, the second substrate includes electrode 2, the insulating film is arranged between electrode 1 and electrode 2, and the insulating film is a cured product of a thermosetting polymer composition.

Abstract: An intelligent teaching and tutoring test method is provided with a remote learning online test mode, a remote learning test paper test mode, a classroom teaching online test mode, and a classroom teaching test paper test mode. Based on the diversified data input methods and intelligent data analyzing process offered by an intelligent teaching and tutoring test system, the invention is a proprietary teaching and tutoring test method for different learners according to their differentiated individual learning situations so as to substantially enhance the learning efficiency of the learners.

Abstract: An interactive learning management method includes abilities to automatically establish group settings on the learning communication mobile application based on the user identities, and to conduct real-time information transmission of class announcements, test paper scores, tutor comments and replies etc, to carry out learning interactions with the teacher by recording video clips of questions and answers, and to download mobile applications for learning via the Internet. The method provides a realization for transmission of learning information and archive photos by the users on the mobile device end through the learning communication mobile application and for downloading remote learning-oriented mobile applications for use, so that users can conduct real-time information notifications or learning through the mobile applications oriented to specific courses on the mobile device without limit of time and place. As a result, learning efficiency can be greatly increased.