Patents by Inventor Chien-Chung Chen

Chien-Chung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190081703
    Abstract: A compact system for active co-boresight measurement includes a detector, a steering mirror, and a controller. The detector detects a portion of a transmission beam emitted by a transceiver and a portion of a received beam that is received from a remote terminal. The controller measures an offset between the detected portion of the received beam and the detected portion of the transmission beam. The controller controls a position of the steering mirror to align the portion of the received beam with a defined position on the detector, the defined position based in part on the offset.
    Type: Application
    Filed: September 14, 2017
    Publication date: March 14, 2019
    Inventors: Eric Douglas Miller, Kevin Michael Birnbaum, Chien-Chung Chen, Andrew Todd Grier
  • Patent number: 10170070
    Abstract: The present invention provides a display apparatus, including: a display panel circuit which includes a panel load line and performs a scanning display operation; and a panel driving circuit. The panel driving circuit determines at least a test phase and a scanning display phase according to a display control signal generated by a timing control circuit, wherein the test phase is a partial time period when the panel driving circuit does not perform the scanning display operation. The panel driving circuit generates a test driving signal on the panel load line, and detects an electronic characteristic of the display panel circuit so as to determine a failure item thereof during the test phase according to a pre-determined test instruction. The panel driving circuit generates a display driving signal on the panel load line for the scanning display operation according to the display control signal during the scanning display phase.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: January 1, 2019
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Chien-Chung Chen, Hsing--Shen Huang
  • Publication number: 20180374744
    Abstract: Formation methods of a semiconductor device structure are provided. A method includes forming a dielectric layer over a first conductive feature and a second conductive feature. The method also includes depositing a conformal layer in a first via hole and a second via hole in the dielectric layer. The method further includes removing the conformal layer in the second via hole. The dielectric layer remains covered by the conformal layer in the first via hole. In addition, the method includes etching the conformal layer in the first via hole and the dielectric layer until the first conductive feature and the second conductive feature become exposed through the first via hole and the second via hole, respectively. The method also includes forming a third conductive feature in the first via hole and a fourth conductive feature in the second via hole.
    Type: Application
    Filed: June 27, 2017
    Publication date: December 27, 2018
    Inventors: Chung-Wen WU, Chien-Wen CHIU, Chien-Chung CHEN, Shiu-Ko JANGJIAN
  • Patent number: 10163465
    Abstract: A data receiver for a double data rate (DDR) memory includes a first stage circuit and a second stage circuit. The first stage circuit is deployed for receiving a single-ended signal from the DDR memory and converting the single-ended signal into a pair of differential signals. The second stage circuit, coupled to the first stage circuit, is deployed for receiving the differential signals from the first stage circuit and converting the differential signals into an output signal. Both of the first stage circuit and the second stage circuit are implemented in a core voltage domain.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: December 25, 2018
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Po-Yao Ko, Chien-Chung Chen, Hsu-Yu Huang, Chun-Po Huang
  • Publication number: 20180366082
    Abstract: A display apparatus includes a timing controller and a gate-driver on array (GOA) control circuit. The timing controller generates a frame synchronization signal. The GOA control circuit is coupled to the timing controller and includes a scan signal management circuit and a level shifter. The scan signal management circuit generates a scan signal management signal according to the frame synchronization signal, a predetermined panel parameter, and an operation clock signal. The scan signal management circuit includes a storage unit which stores the predetermined panel parameter. The level shifter generates a scan control signal according to the scan signal management signal to control a GOA of a display panel circuit. The GOA generates a gate driving signal to control a vertical scan operation of the display panel circuit.
    Type: Application
    Filed: May 15, 2018
    Publication date: December 20, 2018
    Inventors: Chien-Chung Chen, Hsing-Shen Huang
  • Patent number: 10155586
    Abstract: In one embodiment, a system includes a laser configured to generate a laser beam and a laser-aiming module configured to aim the laser beam to be at least in part incident on a remotely located, continuously moving solar cell. The system also includes a controller configured to receive a feedback signal indicating a position of the laser beam relative to the remotely located, continuously moving solar cell and instruct the laser-aiming module to adjust the aiming of the laser beam based on the feedback signal.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: December 18, 2018
    Assignee: Facebook, Inc.
    Inventors: Zhang Liu, Chien-Chung Chen
  • Patent number: 10148362
    Abstract: Optical communication systems and methods using coherently combined optical beams are disclosed. A representative system includes a first mirror having a first actuator for adjusting a position of the first mirror in a path of a first optical beam and a first optical detector for receiving light reflected from the first mirror. The system also includes a second mirror having a second actuator for adjusting a position of the second mirror in a path of a second optical beam and a second optical detector for receiving light reflected from the second mirror. The system includes an interferometer for measuring an interference between the first and second optical beams and a third optical detector for receiving light from the second interfered optical beam. Intensity of the first interfered optical beam is increased by the interference, and intensity of the second interfered optical beam is decreased by the interference.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: December 4, 2018
    Assignee: Facebook, Inc.
    Inventors: Kevin Michael Birnbaum, Chien-Chung Chen
  • Patent number: 10123102
    Abstract: A speaker module is provided. The speaker module includes a housing, a speaker unit, and a modulating unit. The housing has a main segment and an extension segment connecting to the main segment and extending away from the main segment, the main segment and the extension segment communicate with each other and form a chamber. The speaker unit is disposed in the housing in a position that is relative to the main segment. The modulating unit is arranged to correspond to the extension segment and is positioned in the housing. The shape of a cross section of the modulating unit is compatible with the shape of a cross section of the extension segment, and a length between the speaker unit and the modulating unit along the chamber is greater than 0.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: November 6, 2018
    Assignee: ACER INCORPORATED
    Inventors: Ming-Chun Fang, Jia-Ren Chang, Chien-Chung Chen
  • Patent number: 10104467
    Abstract: A speaker device includes a first cabinet, a speaker unit, a second cabinet and a tube cabinet. The first cabinet is disposed in a casing and with a first chamber formed therein. The speaker unit is disposed in the first chamber. The second cabinet is connected to the casing and with an opening formed on the casing. The second cabinet has a second chamber formed therein and communicating with the opening. The tube cabinet connects the first cabinet and the second cabinet. The tube cabinet has a tube chamber formed therein and communicating with the first chamber and the second chamber. A sound generated by the speaker unit is enhanced in the first chamber, transmitted to the second chamber via the tube chamber and emitted out via the opening.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: October 16, 2018
    Assignee: ACER INCORPORATED
    Inventors: Feng-Ming Liu, Jia-Ren Chang, Chih-Hsueh Huang, Chien-Chung Chen
  • Patent number: 10090298
    Abstract: An integrated packaging structure is provided. In the package structure, an integrated component body has a first source region, a second source region, a first setting region, and a second setting region, which are separated from each other. A first MOSFET die and a second MOSFET die are located on the first setting region and the second setting region respectively, and have a top surface, a source electrode pad and a gate electrode pad. The source electrode pad and the gate electrode pad are exposed from the top surface and spaced apart from each other. A first source connection element is connected to the source electrode pad of the first MOSFET die and the first source region. A second source connection element is connected to the source electrode pad of the second MOSFET die and the second source region. A gate connection element is connected to the gate electrode pad and a gate region of the integrated component body.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: October 2, 2018
    Assignee: TAIWAN SEMICONDUCTOR CO., LTD.
    Inventors: Chien-Chung Chen, Sen Mao, Hsin-Liang Lin
  • Patent number: 10056355
    Abstract: A common-source type package structure is provided in the present invention. In the package structure, an integrated component body is configured a common-source pin region, a first arrangement region and a second arrangement region. The second and first arrangement regions are spaced apart from each other. A first MOSFET die and a second MOSFET are respectively located at the first and second arrangement region respectively, and have a top surface, a source electrode pad and a gate electrode pad. The source electrode pad and the gate electrode pad are exposed to the top surface and spaced apart from each other. A common-source connection element is connected to the source electrode pad and the common-source pin region. A gate connection element is connected to the gate electrode pad and a gate pin region of the integrated component body.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: August 21, 2018
    Assignee: Taiwan Semiconductor Co., Ltd.
    Inventors: Chien-Chung Chen, Sen Mao, Hsin-Liang Lin
  • Publication number: 20180211953
    Abstract: An integrated packaging structure is provided. In the package structure, an integrated component body has a first source region, a second source region, a first setting region, and a second setting region, which are separated from each other. A first MOSFET die and a second MOSFET die are located on the first setting region and the second setting region respectively, and have a top surface, a source electrode pad and a gate electrode pad. The source electrode pad and the gate electrode pad are exposed from the top surface and spaced apart from each other. A first source connection element is connected to the source electrode pad of the first MOSFET die and the first source region. A second source connection element is connected to the source electrode pad of the second MOSFET die and the second source region. A gate connection element is connected to the gate electrode pad and a gate region of the integrated component body.
    Type: Application
    Filed: March 2, 2017
    Publication date: July 26, 2018
    Inventors: Chien-Chung CHEN, Sen MAO, Hsin-Liang LIN
  • Publication number: 20180207038
    Abstract: Disclosed is material saving clothing including a repeatedly usable general-purpose holding and looping member for replacement with a full-pad type or a partial-pad type absorbent article and an absorbent article. The holding and looping member has a rear waist portion that is provided with a rear opening and a rear clamp section and a front portion that is provided with a front opening and a front clamping section. The front portion is provided, on a lower portion of each of left and right sides thereof, with a side clamp section and anti-skidding glue. The absorbent article is provided, above a rear end thereof, with left and right rear pulling sections positionable into a rear opening and clamped (from opposite sides) by a rear clamp section and a front clamping section provided above a front end to be pulled through a front opening for clamping by a front clamping section.
    Type: Application
    Filed: March 31, 2017
    Publication date: July 26, 2018
    Inventor: CHIEN-CHUNG CHEN
  • Publication number: 20180197498
    Abstract: The present invention provides a display apparatus, including: a display panel circuit which includes a panel load line and performs a scanning display operation; and a panel driving circuit. The panel driving circuit determines at least a test phase and a scanning display phase according to a display control signal generated by a timing control circuit, wherein the test phase is a partial time period when the panel driving circuit does not perform the scanning display operation. The panel driving circuit generates a test driving signal on the panel load line, and detects an electronic characteristic of the display panel circuit so as to determine a failure item thereof during the test phase according to a pre-determined test instruction. The panel driving circuit generates a display driving signal on the panel load line for the scanning display operation according to the display control signal during the scanning display phase.
    Type: Application
    Filed: March 8, 2018
    Publication date: July 12, 2018
    Inventors: Chien-Chung Chen, Hsing--Shen Huang
  • Patent number: 10004649
    Abstract: The pants has two zippers symmetrically arranged from a waistband's front center extend slantwise downward to a lateral side of the pants. A detachable wrapping member is integrated with the pants. The wrapping member has a belt whose two ends thread through corresponding loops at bottom corners of the wrapping member, and a bottom portion of the wrapping member is flipped upward to reliably cover a crotch area of a user, preventing excrement or urine from overflowing. A clamping member uses Velcro fastening elements or snap buttons to lock a planar object of an absorbent member, and the clamping member can provide secured positioning, increased friction, and load distribution so that the absorbent member can be reliably worn. The clamping member contains a clamping element that is concealed when not in use. The clamping element then can be flipped to further secure its locking the absorbent member.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: June 26, 2018
    Inventor: Chien-Chung Chen
  • Publication number: 20180166423
    Abstract: A common-source type package structure is provided in the present invention. In the package structure, an integrated component body is configured a common-source pin region, a first arrangement region and a second arrangement region. The second and first arrangement regions are spaced apart from each other. A first MOSFET die and a second MOSFET are respectively located at the first and second arrangement region respectively, and have a top surface, a source electrode pad and a gate electrode pad. The source electrode pad and the gate electrode pad are exposed to the top surface and spaced apart from each other. A common-source connection element is connected to the source electrode pad and the common-source pin region. A gate connection element is connected to the gate electrode pad and a gate pin region of the integrated component body.
    Type: Application
    Filed: November 3, 2017
    Publication date: June 14, 2018
    Inventors: Chien-Chung CHEN, Sen MAO, Hsin-Liang LIN
  • Publication number: 20180166422
    Abstract: A common-source type package structure is provided in the present invention. In the package structure, an integrated component body is configured a common-source pin region, a first arrangement region and a second arrangement region. The second and first arrangement regions are spaced apart from each other. A first MOSFET die and a second MOSFET are respectively located at the first and second arrangement region respectively, and have a top surface, a source electrode pad and a gate electrode pad. The source electrode pad and the gate electrode pad are exposed to the top surface and spaced apart from each other. A common-source connection element is connected to the source electrode pad and the common-source pin region. A gate connection element is connected to the gate electrode pad and a gate pin region of the integrated component body.
    Type: Application
    Filed: February 22, 2017
    Publication date: June 14, 2018
    Inventors: Chien-Chung CHEN, Sen MAO, Hsin-Liang LIN
  • Patent number: 9997500
    Abstract: A common-source type package structure is provided in the present invention. In the package structure, an integrated component body is configured a common-source pin region, a first arrangement region and a second arrangement region. The second and first arrangement regions are spaced apart from each other. A first MOSFET die and a second MOSFET are respectively located at the first and second arrangement region respectively, and have a top surface, a source electrode pad and a gate electrode pad. The source electrode pad and the gate electrode pad are exposed to the top surface and spaced apart from each other. A common-source connection element is connected to the source electrode pad and the common-source pin region. A gate connection element is connected to the gate electrode pad and a gate pin region of the integrated component body.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: June 12, 2018
    Assignee: TAIWAN SEMICONDUCTOR CO., LTD.
    Inventors: Chien-Chung Chen, Sen Mao, Hsin-Liang Lin
  • Patent number: 9947283
    Abstract: The present invention provides a display apparatus, including: a display panel circuit which includes a panel load line and performs a scanning display operation; and a panel driving circuit. The panel driving circuit determines at least a test phase and a scanning display phase according to a display control signal generated by a timing control circuit, wherein the test phase is a partial time period when the panel driving circuit does not perform the scanning display operation. The panel driving circuit generates a test driving signal on the panel load line, and detects an electronic characteristic of the display panel circuit so as to determine a failure item thereof during the test phase according to a pre-determined test instruction. The panel driving circuit generates a display driving signal on the panel load line for the scanning display operation according to the display control signal during the scanning display phase.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: April 17, 2018
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Chien-Chung Chen, Hsing-Shen Huang
  • Publication number: 20180102283
    Abstract: An interconnection structure includes a first dielectric layer, a bottom conductive feature present in the first dielectric layer, a second dielectric layer present on the first dielectric layer, an aluminum-containing etch stop layer present between the first dielectric layer and the second dielectric layer, an upper conductive via present at least in the second dielectric layer and electrically connected to the bottom conductive feature, and at least one aluminum-containing fragment present at least at a bottom corner of the upper conductive via.
    Type: Application
    Filed: December 4, 2017
    Publication date: April 12, 2018
    Inventors: Chung-Wen Wu, Shiu-Ko Jangjian, Chien-Wen Chiu, Chien-Chung Chen