Patents by Inventor Chien-Fan Chen
Chien-Fan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240164021Abstract: A manufacturing method of an embedded component package structure includes the following steps: providing a carrier and forming a semi-cured first dielectric layer on the carrier, the semi-cured first dielectric layer having a first surface; providing a component on the semi-cured first dielectric layer, and respectively providing heat energies from a top and a bottom of the component to cure the semi-cured first dielectric layer; forming a second dielectric layer on the first dielectric layer to cover the component; and forming a patterned circuit layer on the second dielectric layer, the patterned circuit layer being electrically connected to the component.Type: ApplicationFiled: January 23, 2024Publication date: May 16, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chien-Fan CHEN, Chien-Hao WANG
-
Patent number: 11947153Abstract: A backlight module and a display device are provided, and the backlight module includes a light guide plate, a plurality of light-emitting components, and a frame. The light guide plate includes a first side, a second side, and two third sides. The light-emitting components are disposed on the first side, and light generated from the light-emitting components enters the light guide plate from the first side. The frame covers the second side and the third sides and includes an opening and at least one buffer portion. The light-emitting components are disposed in the opening, and the buffer portion is disposed on a side of the opening and contacts the light guide plate.Type: GrantFiled: May 4, 2023Date of Patent: April 2, 2024Assignee: Radiant Opto-Electronics CorporationInventors: Hung-Pin Cheng, Shih-Fan Liu, Chien-Yu Ko, Jui-Lin Chen
-
Patent number: 11940828Abstract: A voltage tracking circuit is provided. The voltage tracking circuit includes first and second P-type transistors and a control circuit. The drain of the first P-type transistor is coupled to a first voltage terminal. The gate and the drain of the second P-type transistor are respectively coupled to the first voltage terminal and a second voltage terminal. The control circuit is coupled to the first and second voltage terminals and generates a control voltage according to the first voltage and the second voltage. The sources of the first and second P-type transistors are coupled to an output terminal of the voltage tracking circuit, and the output voltage is generated at the output terminal. In response to the second voltage being higher than the first voltage, the control circuit generates the control signal to turn off the first P-type transistor.Type: GrantFiled: August 17, 2022Date of Patent: March 26, 2024Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Shao-Chang Huang, Yeh-Ning Jou, Ching-Ho Li, Kai-Chieh Hsu, Chun-Chih Chen, Chien-Wei Wang, Gong-Kai Lin, Li-Fan Chen
-
Patent number: 11923285Abstract: An electronic device package and a method for manufacturing the same are provided. The electronic device package includes a circuit layer and an electronic component. The circuit layer includes a dielectric layer having an opening, and an electrical contact. A width of an aperture of the opening increases from a first surface toward a second surface. The electrical contact is at least partially disposed in the opening and exposed through the opening. The electronic component is disposed on the second surface and electrically connected to the circuit layer.Type: GrantFiled: January 5, 2021Date of Patent: March 5, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Po-Jen Cheng, Chien-Fan Chen
-
Patent number: 11882660Abstract: A manufacturing method of an embedded component package structure includes the following steps: providing a carrier and forming a semi-cured first dielectric layer on the carrier, the semi-cured first dielectric layer having a first surface; providing a component on the semi-cured first dielectric layer, and respectively providing heat energies from a top and a bottom of the component to cure the semi-cured first dielectric layer; forming a second dielectric layer on the first dielectric layer to cover the component; and forming a patterned circuit layer on the second dielectric layer, the patterned circuit layer being electrically connected to the component.Type: GrantFiled: January 10, 2023Date of Patent: January 23, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chien-Fan Chen, Chien-Hao Wang
-
Publication number: 20230327446Abstract: The present disclosure provides an energy storage system. For example, an energy storage system comprises a chassis and a printed circuit board assembly connected to the chassis and comprising a connecting/disconnecting device configured to connect to a corresponding connecting/disconnecting device on the battery cell for enabling connection of the battery cell to the chassis.Type: ApplicationFiled: April 8, 2022Publication date: October 12, 2023Inventors: Wei JIANG, Chien-Fan CHEN, Christopher McNair LYKE, Chris Morrow YOUNG
-
Patent number: 11587881Abstract: A substrate structure is disclosed. The substrate structure includes a carrier, a dielectric layer on the carrier, a patterned organic core layer in the dielectric layer, and a conductive via. The patterned organic core layer defines a passage extending in the dielectric layer towards the carrier. The conductive via extends through the passage towards the carrier without contacting the patterned organic core layer.Type: GrantFiled: March 9, 2020Date of Patent: February 21, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chien-Fan Chen, Yu-Ju Liao, Chu-Jie Yang, Sheng-Hung Shih
-
Patent number: 11553596Abstract: A manufacturing method of an embedded component package structure includes the following steps: providing a carrier and forming a semi-cured first dielectric layer on the carrier, the semi-cured first dielectric layer having a first surface; providing a component on the semi-cured first dielectric layer, and respectively providing heat energies from a top and a bottom of the component to cure the semi-cured first dielectric layer; forming a second dielectric layer on the first dielectric layer to cover the component; and forming a patterned circuit layer on the second dielectric layer, the patterned circuit layer being electrically connected to the component.Type: GrantFiled: June 8, 2021Date of Patent: January 10, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chien-Fan Chen, Chien-Hao Wang
-
Publication number: 20220278052Abstract: The present disclosure provides a substrate structure. The substrate structure includes an interconnection structure, a dielectric layer on the interconnection structure, an electronic component embedded in the dielectric layer, and a first conductive via penetrating through the dielectric layer and disposed adjacent to the electronic component. The interconnection structure includes a carrier having a first surface and a second surface opposite to the first surface, a first conductive layer disposed on the first surface of the carrier, and a second conductive layer disposed on the second surface of the carrier. The first conductive via and at least one of the first conductive layer and the second conductive layer define a first shielding structure surrounding the electronic component. A method of manufacturing a substrate structure is also disclosed.Type: ApplicationFiled: May 17, 2022Publication date: September 1, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chien-Fan CHEN, Yu-Ju LIAO
-
Publication number: 20220216136Abstract: An electronic device package and a method for manufacturing the same are provided. The electronic device package includes a circuit layer and an electronic component. The circuit layer includes a dielectric layer having an opening, and an electrical contact. A width of an aperture of the opening increases from a first surface toward a second surface. The electrical contact is at least partially disposed in the opening and exposed through the opening. The electronic component is disposed on the second surface and electrically connected to the circuit layer.Type: ApplicationFiled: January 5, 2021Publication date: July 7, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Po-Jen CHENG, Chien-Fan CHEN
-
Patent number: 11335646Abstract: The present disclosure provides a substrate structure. The substrate structure includes an interconnection structure, a dielectric layer on the interconnection structure, an electronic component embedded in the dielectric layer, and a first conductive via penetrating through the dielectric layer and disposed adjacent to the electronic component. The interconnection structure includes a carrier having a first surface and a second surface opposite to the first surface, a first conductive layer disposed on the first surface of the carrier, and a second conductive layer disposed on the second surface of the carrier. The first conductive via and at least one of the first conductive layer and the second conductive layer define a first shielding structure surrounding the electronic component. A method of manufacturing a substrate structure is also disclosed.Type: GrantFiled: March 10, 2020Date of Patent: May 17, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chien-Fan Chen, Yu-Ju Liao
-
Patent number: 11296030Abstract: An embedded component package structure including a dielectric structure, a semiconductor chip, a first polymer layer, and a patterned conductive layer is provided. The semiconductor chip is embedded in the dielectric structure. The first polymer layer covers the semiconductor chip and has a first thickness, and the first thickness is greater than a second thickness of the dielectric structure above the first polymer layer. The patterned conductive layer covers an upper surface of the dielectric structure and extends over the first polymer layer, and the patterned conductive layer is electrically connected to the semiconductor chip.Type: GrantFiled: April 29, 2019Date of Patent: April 5, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yu-Ju Liao, Chien-Fan Chen, Chien-Hao Wang
-
Embedded component package structure, embedded type panel substrate and manufacturing method thereof
Patent number: 11277917Abstract: An embedded component package structure including a circuit substrate, an embedded component and a stress compensation layer is provided. The circuit substrate includes a core layer and an asymmetric circuit structure, and the core layer has a first thickness. The embedded component is disposed in the core layer. The stress compensation layer is disposed on one side of the core layer, and the stress compensation layer has a second thickness between 4 ?m and 351 ?m.Type: GrantFiled: March 12, 2019Date of Patent: March 15, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yu-Ju Liao, Chien-Fan Chen, Chien-Hao Wang, I-Chia Lin -
Patent number: 11228071Abstract: A battery cell of a battery pack to power an electric vehicle can include a housing to at least partially enclose an electrode assembly is provided. The battery cell can include a vent plate coupled with the housing via a glass weld at a lateral end of the battery cell. The vent plate can include a scoring pattern to cause the vent plate to rupture in response to a threshold pressure. A first end of a polymer tab can be electrically coupled with the vent plate at an area within a scored region defined by the scoring pattern. A second end of the polymer tab can be electrically coupled with an electrode assembly. The polymer tab can melt in response to either a threshold temperature or a threshold current within the battery cell.Type: GrantFiled: July 24, 2020Date of Patent: January 18, 2022Assignees: CHONGQING JINKANG NEW ENERGY VEHICLE CO., LTD., SF MOTORS, INC.Inventors: Ying Liu, Scott Quinlan Freeman Monismith, Chien-Fan Chen, Jeremy Andrew Elsberry, Yifan Tang
-
Patent number: 11139179Abstract: An embedded component package structure including a dielectric structure, a semiconductor chip and a patterned conductive layer is provided. The semiconductor chip is embedded in the dielectric structure, and the dielectric structure encapsulates the semiconductor chip and has a first thickness. The semiconductor chip having a second thickness, and the first thickness is greater than the second thickness, and a ratio of the first thickness to the second thickness is between 1.1 and 28.4. The patterned conductive layer covers an upper surface of the dielectric structure and extending into a first opening of the dielectric structure. The first opening exposes an electrical pad of the semiconductor chip, and the patterned conductive layer is electrically connected to the electrical pad of the semiconductor chip.Type: GrantFiled: September 9, 2019Date of Patent: October 5, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chien-Fan Chen, Yu-Ju Liao
-
Publication number: 20210298176Abstract: A manufacturing method of an embedded component package structure includes the following steps: providing a carrier and forming a semi-cured first dielectric layer on the carrier, the semi-cured first dielectric layer having a first surface; providing a component on the semi-cured first dielectric layer, and respectively providing heat energies from a top and a bottom of the component to cure the semi-cured first dielectric layer; forming a second dielectric layer on the first dielectric layer to cover the component; and forming a patterned circuit layer on the second dielectric layer, the patterned circuit layer being electrically connected to the component.Type: ApplicationFiled: June 8, 2021Publication date: September 23, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chien-Fan CHEN, Chien-Hao WANG
-
Publication number: 20210287997Abstract: The present disclosure provides a substrate structure. The substrate structure includes an interconnection structure, a dielectric layer on the interconnection structure, an electronic component embedded in the dielectric layer, and a first conductive via penetrating through the dielectric layer and disposed adjacent to the electronic component. The interconnection structure includes a carrier having a first surface and a second surface opposite to the first surface, a first conductive layer disposed on the first surface of the carrier, and a second conductive layer disposed on the second surface of the carrier. The first conductive via and at least one of the first conductive layer and the second conductive layer define a first shielding structure surrounding the electronic component. A method of manufacturing a substrate structure is also disclosed.Type: ApplicationFiled: March 10, 2020Publication date: September 16, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chien-Fan CHEN, Yu-Ju LIAO
-
Publication number: 20210280521Abstract: A substrate structure is disclosed. The substrate structure includes a carrier, a dielectric layer on the carrier, a patterned organic core layer in the dielectric layer, and a conductive via. The patterned organic core layer defines a passage extending in the dielectric layer towards the carrier. The conductive via extends through the passage towards the carrier without contacting the patterned organic core layer.Type: ApplicationFiled: March 9, 2020Publication date: September 9, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chien-Fan CHEN, Yu-Ju LIAO, Chu-Jie YANG, Sheng-Hung SHIH
-
Patent number: 11032911Abstract: A manufacturing method of an embedded component package structure includes the following steps: providing a carrier and forming a semi-cured first dielectric layer on the carrier, the semi-cured first dielectric layer having a first surface; providing a component on the semi-cured first dielectric layer, and respectively providing heat energies from a top and a bottom of the component to cure the semi-cured first dielectric layer; forming a second dielectric layer on the first dielectric layer to cover the component; and forming a patterned circuit layer on the second dielectric layer, the patterned circuit layer being electrically connected to the component.Type: GrantFiled: July 29, 2020Date of Patent: June 8, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chien-Fan Chen, Chien-Hao Wang
-
Publication number: 20210143467Abstract: A system for a high temperature, high energy density secondary battery that includes an electrolyte comprising an ionic liquid solvent, and electrolyte salts; a metallic anode; a cathode, compatible with the electrolyte and comprising an active material and a polyimide binder; and a separator component that separates the cathode and anode.Type: ApplicationFiled: September 15, 2020Publication date: May 13, 2021Inventors: Richard Y. Wang, Mauro Pasta, Olivia Risset, Chien-Fan Chen