Patents by Inventor Chien-Feng Chan
Chien-Feng Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11216030Abstract: A portable electronic device includes a host, a sliding base, a base plate, a display and a sliding rotating element. The sliding base is disposed on the host and has at least one guiding portion and at least one sliding slot connected to the guiding portion. The base plate is disposed on the sliding base. The display is pivoted on the base plate. The sliding rotating element is fixed to the base plate and is rotatably and slidably connected to the sliding base, and the display and the base plate are configured to rotate or slide on the sliding base along with the sliding rotating element.Type: GrantFiled: September 7, 2020Date of Patent: January 4, 2022Assignee: COMPAL ELECTRONICS, INC.Inventors: Yan-Yu Chen, Chien-Feng Chan, Ming-Cheng Tsou, Yu-Wen Cheng, Chun-Wen Wang, Wang-Hung Yeh
-
Patent number: 11145621Abstract: A semiconductor package device comprises a substrate, a first electronic component, a first encapsulant, a second electronic component, and a first conductive trace. The substrate has a first surface. The first electronic component is on the first surface of the substrate. The first encapsulant is on the first surface of the substrate and covers the first electronic component. The second electronic component is on the first encapsulant. The first conductive trace is within the first encapsulant. The first conductive trace is electrically connected to the second electronic component.Type: GrantFiled: June 6, 2018Date of Patent: October 12, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Jr-Wei Lin, Chia-Cheng Liu, Chien-Feng Chan
-
Publication number: 20210089084Abstract: A portable electronic device includes a host, a sliding base, a base plate, a display and a sliding rotating element. The sliding base is disposed on the host and has at least one guiding portion and at least one sliding slot connected to the guiding portion. The base plate is disposed on the sliding base. The display is pivoted on the base plate. The sliding rotating element is fixed to the base plate and is rotatably and slidably connected to the sliding base, and the display and the base plate are configured to rotate or slide on the sliding base along with the sliding rotating element.Type: ApplicationFiled: September 7, 2020Publication date: March 25, 2021Applicant: COMPAL ELECTRONICS, INC.Inventors: Yan-Yu Chen, Chien-Feng Chan, Ming-Cheng Tsou, Yu-Wen Cheng, Chun-Wen Wang, Wang-Hung Yeh
-
Patent number: 10936020Abstract: An electronic device includes a base, a lifting mechanism, a body and a switching mechanism. The lifting mechanism and the body are movably disposed at the base. The lifting mechanism is located between the body and the base, and two ends of the lifting mechanism are connected to the body and the base. The switching mechanism is disposed at the base. The switching mechanism is configured to lock the body and the lifting mechanism to the base or configured to remove a locking relationship of the body and the lifting mechanism with respect to the base. An expansion device is further provided.Type: GrantFiled: August 22, 2019Date of Patent: March 2, 2021Assignee: COMPAL ELECTRONICS, INC.Inventors: Ching-Shiang Chang, Tung-Ying Wu, Wang-Hung Yeh, Po-Hsuan Wang, Chien-Feng Chan, Ming-Cheng Tsou
-
Publication number: 20200098700Abstract: A semiconductor package device includes a substrate, a sealant, a trench, a spacer and a conductive material. The substrate includes a first surface, a second surface opposite the first surface, and a lateral surface extending from the first surface to the second surface. The sealant is disposed on the first surface of the substrate and includes a first surface and a second surface opposite the first surface. The trench passes through the sealant and includes a first portion adjacent to the first surface of the sealant and a second portion between the first portion and the substrate. A width of the first portion is greater than a width of the second portion. The spacer is disposed in the trench and in contact with the sealant. The conductive material is disposed in the trench and encapsulates the spacer.Type: ApplicationFiled: September 21, 2018Publication date: March 26, 2020Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Jr-Wei LIN, Chien-Feng CHAN
-
Publication number: 20200081498Abstract: An electronic device includes a base, a lifting mechanism, a body and a switching mechanism. The lifting mechanism and the body are movably disposed at the base. The lifting mechanism is located between the body and the base, and two ends of the lifting mechanism are connected to the body and the base. The switching mechanism is disposed at the base. The switching mechanism is configured to lock the body and the lifting mechanism to the base or configured to remove a locking relationship of the body and the lifting mechanism with respect to the base. An expansion device is further provided.Type: ApplicationFiled: August 22, 2019Publication date: March 12, 2020Applicant: COMPAL ELECTRONICS, INC.Inventors: Ching-Shiang Chang, Tung-Ying Wu, Wang-Hung Yeh, Po-Hsuan Wang, Chien-Feng Chan, Ming-Cheng Tsou
-
Publication number: 20190378817Abstract: A semiconductor package device comprises a substrate, a first electronic component, a first encapsulant, a second electronic component, and a first conductive trace. The substrate has a first surface. The first electronic component is on the first surface of the substrate. The first encapsulant is on the first surface of the substrate and covers the first electronic component. The second electronic component is on the first encapsulant. The first conductive trace is within the first encapsulant. The first conductive trace is electrically connected to the second electronic component.Type: ApplicationFiled: June 6, 2018Publication date: December 12, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Jr-Wei LIN, Chia-Cheng LIU, Chien-Feng CHAN
-
Patent number: 9349705Abstract: A conductive bump structure used to be formed on a substrate having a plurality of bonding pads. The conductive bump structure includes a first metal layer formed on the bonding pads, a second metal layer formed on the first metal layer, and a third metal layer formed on the second metal layer. The second metal layer has a second melting point higher than a third melting point of the third metal layer. Therefore, a thermal compression bonding process is allowed to be performed to the third metal layer first so as to bond the substrate to another substrate, and then a reflow process can be performed to melt the second metal layer and the third metal layer into each other so as to form an alloy portion, thus avoiding cracking of the substrate.Type: GrantFiled: February 6, 2015Date of Patent: May 24, 2016Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chien-Feng Chan, Mu-Hsuan Chan, Chun-Tang Lin, Yi-Che Lai
-
Patent number: 9269693Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor chip having opposite first and second surfaces; an RDL structure formed on the first surface of the semiconductor chip and having opposite third and fourth surfaces and a plurality of first conductive through holes penetrating the third and fourth surfaces thereof, wherein the RDL structure is formed on the semiconductor chip through the fourth surface thereof and electrically connected to the semiconductor chip through a plurality of first conductive elements, and the third surface of the RDL structure has a redistribution layer formed thereon; a plurality of conductive bumps formed on the redistribution layer; and an encapsulant formed on the first surface of the semiconductor chip for encapsulating the RDL structure, wherein the conductive bumps are embedded in and exposed from the encapsulant. The invention effectively prevents warpage of the semiconductor package and improves the electrical connection significantly.Type: GrantFiled: January 23, 2015Date of Patent: February 23, 2016Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chien-Feng Chan, Chun-Tang Lin, Yi-Che Lai
-
Publication number: 20150155258Abstract: A conductive bump structure used to be formed on a substrate having a plurality of bonding pads. The conductive bump structure includes a first metal layer formed on the bonding pads, a second metal layer formed on the first metal layer, and a third metal layer formed on the second metal layer. The second metal layer has a second melting point higher than a third melting point of the third metal layer. Therefore, a thermal compression bonding process is allowed to be performed to the third metal layer first so as to bond the substrate to another substrate, and then a reflow process can be performed to melt the second metal layer and the third metal layer into each other so as to form an alloy portion, thus avoiding cracking of the substrate.Type: ApplicationFiled: February 6, 2015Publication date: June 4, 2015Inventors: Chien-Feng Chan, Mu-Hsuan Chan, Chun-Tang Lin, Yi-Che Lai
-
Publication number: 20150132893Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor chip having opposite first and second surfaces; an RDL structure formed on the first surface of the semiconductor chip and having opposite third and fourth surfaces and a plurality of first conductive through holes penetrating the third and fourth surfaces thereof, wherein the RDL structure is formed on the semiconductor chip through the fourth surface thereof and electrically connected to the semiconductor chip through a plurality of first conductive elements, and the third surface of the RDL structure has a redistribution layer formed thereon; a plurality of conductive bumps formed on the redistribution layer; and an encapsulant formed on the first surface of the semiconductor chip for encapsulating the RDL structure, wherein the conductive bumps are embedded in and exposed from the encapsulant. The invention effectively prevents warpage of the semiconductor package and improves the electrical connection significantly.Type: ApplicationFiled: January 23, 2015Publication date: May 14, 2015Inventors: Chien-Feng Chan, Chun-Tang Lin, Yi-Che Lai
-
Patent number: 8952537Abstract: A conductive bump structure used to be formed on a substrate having a plurality of bonding pads. The conductive bump structure includes a first metal layer formed on the bonding pads, a second metal layer formed on the first metal layer, and a third metal layer formed on the second metal layer. The second metal layer has a second melting point higher than a third melting point of the third metal layer. Therefore, a thermal compression bonding process is allowed to be performed to the third metal layer first so as to bond the substrate to another substrate, and then a reflow process can be performed to melt the second metal layer and the third metal layer into each other so as to form an alloy portion, thus avoiding cracking of the substrate.Type: GrantFiled: November 15, 2012Date of Patent: February 10, 2015Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chien-Feng Chan, Mu-Hsuan Chan, Chun-Tang Lin, Yi-Che Lai
-
Patent number: 8952528Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor chip having opposite first and second surfaces; an RDL structure formed on the first surface of the semiconductor chip and having opposite third and fourth surfaces and a plurality of first conductive through holes penetrating the third and fourth surfaces thereof, wherein the RDL structure is formed on the semiconductor chip through the fourth surface thereof and electrically connected to the semiconductor chip through a plurality of first conductive elements, and the third surface of the RDL structure has a redistribution layer formed thereon; a plurality of conductive bumps formed on the redistribution layer; and an encapsulant formed on the first surface of the semiconductor chip for encapsulating the RDL structure, wherein the conductive bumps are embedded in and exposed from the encapsulant. The invention effectively prevents warpage of the semiconductor package and improves the electrical connection significantly.Type: GrantFiled: January 30, 2013Date of Patent: February 10, 2015Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chien-Feng Chan, Chun-Tang Lin, Yi Che Lai
-
Publication number: 20140008819Abstract: A substrate structure is provided, including a substrate and a strengthening member bonded to a surface of the substrate. The strengthening member has a CTE (Coefficient of Thermal Expansion) less than that of the substrate so as to effectively prevent warpage from occurring to the substrate structure.Type: ApplicationFiled: October 25, 2012Publication date: January 9, 2014Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chien-Feng Chan, Chun-Tang Lin, Yi-Che Lai
-
Publication number: 20140008787Abstract: A conductive bump structure used to be formed on a substrate having a plurality of bonding pads. The conductive bump structure includes a first metal layer formed on the bonding pads, a second metal layer formed on the first metal layer, and a third metal layer formed on the second metal layer. The second metal layer has a second melting point higher than a third melting point of the third metal layer. Therefore, a thermal compression bonding process is allowed to be performed to the third metal layer first so as to bond the substrate to another substrate, and then a reflow process can be performed to melt the second metal layer and the third metal layer into each other so as to form an alloy portion, thus avoiding cracking of the substrate.Type: ApplicationFiled: November 15, 2012Publication date: January 9, 2014Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chien-Feng Chan, Mu-Hsuan Chan, Chun-Tang Lin, Yi-Che Lai
-
Publication number: 20130256915Abstract: A semiconductor package includes a packaging substrate having a die attach area, a plurality of flow-guiding blocks disposed around an outer periphery of the die attach area, a first semiconductor element mounted on the die attach area, a second semiconductor element mounted on the first semiconductor element, and an underfill formed between the packaging substrate and the second semiconductor element. During filling of the underfill between the packaging substrate and the second semiconductor element, the flow-guiding blocks can guide a portion of the underfill to flow between the first semiconductor element and the second semiconductor element such that only one dispensing process is required for the underfill to completely encapsulate all conductive bumps used for flip-chip interconnection, thereby simplifying the fabrication process and improving the production efficiency.Type: ApplicationFiled: September 13, 2012Publication date: October 3, 2013Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Huei-Nuan Huang, Chun-Tang Lin, Chien-Feng Chan, Chi-Hsin Chiu
-
Publication number: 20070032273Abstract: An accessory utilized in a portable electronic device includes: a housing; a connecting port placed on the housing, for electrically connecting an output port of the portable electronic device in order to receive an audio signal output by the portable electronic device; an audio signal outputting module placed inside the housing and electrically connected to the connecting port, for processing and outputting the audio signal; and a fixing module, placed on the housing, for locking the portable electronic device and the accessory such that the accessory can move with the portable electronic device.Type: ApplicationFiled: January 12, 2006Publication date: February 8, 2007Inventors: Fu-Yuan Hsiao, Chun-Yin Hua, Chien-Feng Chan