Abstract: The present application provides a system for unmanned aerial vehicle (UAV) parachute landing. An exemplary system includes a detector configured to detect at least one of a flight speed, a wind speed, a wind direction, a position, a height, and a voltage of a UAV. The system also includes a memory storing instructions and a processor configured to execute the instructions to cause the system to: determine whether to open a parachute of the UAV in accordance with a criterion, responsive to the determination to open the parachute of the UAV, stop a motor of the UAV that spins a propeller of the UAV, and open the parachute of the UAV after stopping the motor of the UAV for a first period.

Abstract: A wafer grinding parameter optimization method and an electronic device are provided. The method includes the following. A natural frequency of a grinding wheel spindle of wafer processing equipment is obtained, and a grinding stability lobe diagram is generated accordingly. A grinding speed is selected based on a speed range of the grinding wheel spindle. Multiple grinding parameter combinations are determined based on the grinding speed. Multiple grinding simulation result combinations corresponding to the grinding parameter combinations are generated. A specific grinding parameter combination is selected based on each of the grinding simulation result combinations, and the wafer processing equipment is set accordingly.

Abstract: An electronic device includes a substrate, a first transistor, a second transistor and a conductor. The first transistor is disposed on the substrate and comprises an oxide semiconductor layer. The second transistor is disposed on the substrate and comprises a silicon semiconductor layer. The conductor is electrically connected to the oxide semiconductor layer and the silicon semiconductor layer.

Abstract: A display device includes a gate driving circuit and a driving circuit. The gate driving circuit outputs a clock signal. The driving circuit receives the clock signal for driving a display unit and comprises two transistors. Wherein one of the two transistors is an oxide transistor and the other one of the two transistors is a silicon transistor.

Abstract: The disclosure provides an electronic device. The electronic device includes a pixel array and a first driving circuit. The pixel array is disposed on a substrate and includes a plurality of sub-pixel rows. The first driving circuit is disposed on the substrate and located on one side of the pixel array. The first driving circuit includes a plurality of demultiplexer circuits and a plurality of switching circuits. The demultiplexer circuits include a first demultiplexer circuit. The switching circuits include a first switching circuit. The first switching circuit is coupled to the first demultiplexer circuit, and the first demultiplexer circuit is coupled to at least three of the plurality of sub-pixel rows.

Abstract: A display device includes a gate driving circuit and a driving circuit. The gate driving circuit outputs a clock signal. The driving circuit receives the clock signal for driving a display unit and comprises two transistors. Wherein one of the two transistors is an oxide transistor and the other one of the two transistors is a silicon transistor.

Abstract: A gate driving circuit includes a shift unit and a switch unit. The shift unit receives a start input signal, a first clock input signal and a second clock input signal to generate an enable output signal. The switch unit is connected to the shift unit and receiving the enable output signal. The switch unit outputs a third clock signal based on the enable output signal.

Abstract: The disclosure provides an electronic device. The electronic device includes a pixel array and a first driving circuit. The pixel array is disposed on a substrate and includes a plurality of sub-pixel rows. The first driving circuit is disposed on the substrate and located on one side of the pixel array. The first driving circuit includes a plurality of demultiplexer circuits and a plurality of switching circuits. The demultiplexer circuits include a first demultiplexer circuit. The switching circuits include a first switching circuit. The first switching circuit is coupled to the first demultiplexer circuit, and the first demultiplexer circuit is coupled to at least three of the plurality of sub-pixel rows.

Abstract: A display panel includes a first substrate, a second substrate, a display layer, and a driving unit. The first substrate has a display area, an extended area, and an edge area located between the display area and the extended area. The display layer is positioned between the first and second substrates. The length of a boundary line of the edge area and the extended area is greater than the length of a bottom edge of the extended area that is away from the edge area.

Abstract: A gate driving circuit includes a shift unit and a switch unit. The shift unit receives a start input signal, a first clock input signal and a second clock input signal to generate an enable output signal. The switch unit is connected to the shift unit and receiving the enable output signal. The switch unit outputs a third clock signal based on the enable output signal.

Abstract: A gate driving circuit includes a shift unit and a switch unit. The shift unit receives a start input signal, a first clock input signal and a second clock input signal to generate an enable output signal. The switch unit is connected to the shift unit and receiving the enable output signal. The switch unit outputs a third clock signal based on the enable output signal.

Abstract: The invention provides a touch display panel, including: a lower substrate where a common electrode layer, a first test pad, and a second test pad are formed, an upper substrate disposed above the common electrode layer, a liquid crystal layer sandwiched between the upper substrate and lower substrate, wherein the common electrode layer is divided into a plurality of common electrode blocks arranged in a matrix, and any two adjacent common electrode blocks of the plurality of common electrode blocks are coupled to the first test pad and the second test pad, respectively.

Abstract: A display device is disclosed, which comprises: a first substrate; a second substrate disposed adjacent to the first substrate and partially covering the first substrate, wherein the second substrate comprises a second arc edge and a second side, and the second arc edge connects to the second side; a driving unit disposed on a part of the first substrate uncovered with the second substrate; and a compensation panel disposed on the driving unit and comprising a third arc edge and a third side, wherein the third arc edge connects to the third side, wherein the third side corresponds to the second side, and the third arc edge corresponds to the second arc edge.

Abstract: A display panel includes a first substrate, a second substrate, a display layer, and a driving unit. The first substrate has a display area, an extended area, and an edge area located between the display area and the extended area. The display layer is positioned between the first and second substrates. The length of a boundary line of the edge area and the extended area is greater than the length of a bottom edge of the extended area that is away from the edge area.

Abstract: A gate driving circuit includes a shift unit and a switch unit. The shift unit receives a start input signal, a first clock input signal and a second clock input signal to generate an enable output signal. The switch unit is connected to the shift unit and receiving the enable output signal. The switch unit outputs a third clock signal based on the enable output signal.

Abstract: Disclosed is a display apparatus, including a display region and a peripheral region outside of the display region. The display region includes a plurality of pixels arranged on a substrate. The peripheral region includes a plurality of first circuit areas and second circuit areas on the substrate. The first circuit areas drive the pixels in a first direction, and the second circuit areas drive the pixels in a second direction. At least one of the first circuit area and the second circuit area has the shape of a pentagon with sequentially connected sides including a first side, a second side, a third side, a fourth side, and a fifth side.

Abstract: A display panel includes a first substrate, a second substrate, a display layer, and a driving unit. The first substrate has a display area, an extended area, and an edge area located between the display area and the extended area. The display layer is positioned between the first and second substrates. The length of a boundary line of the edge area and the extended area is greater than the length of a bottom edge of the extended area that away from the edge area.

Abstract: A display panel structure includes a substrate, plural gate lines and data lines arranged on the substrate, plural pixel units, and plural dummy pixel units. The substrate has a display region and a peripheral region surrounding the display region. The gate lines and data lines are extended from the display region to the peripheral region. The pixel units are disposed at the display region. The dummy pixel units are disposed at the peripheral region, and include a first region, a second region, and a third region. The dummy pixel units of the first region and the second region are arranged along a first direction and a second direction, respectively. The dummy pixel units of the third region are arranged between the first and second regions. The dummy pixel units of the third region include one of the gate lines and one of the data lines.

Abstract: The invention provides a touch display panel, including: a lower substrate where a common electrode layer, a first test pad, and a second test pad are formed, an upper substrate disposed above the common electrode layer, a liquid crystal layer sandwiched between the upper substrate and lower substrate, wherein the common electrode layer is divided into a plurality of common electrode blocks arranged in a matrix, and any two adjacent common electrode blocks of the plurality of common electrode blocks are coupled to the first test pad and the second test pad, respectively.

Abstract: A display panel is disclosed, having a display region and a non-display region out of the display region, wherein the display region comprises a central pixel region and a border pixel region disposed between the central pixel region and the non-display region, the display panel comprising: a first substrate; a second substrate; a display medium layer; a plurality of central pixel units located at the central pixel region and having a plurality of first electrodes disposed on the second substrate; and a plurality of border pixel units located at the border pixel region and having a plurality of second electrodes disposed on the second substrate; wherein outmost edges of a part of the adjacent border pixel units form a ladder-like shape, and a light output area of at least one of the border pixel units is smaller than that of at least one of the central pixel units.