Abstract: A frequency calibration (FCAL) circuit and a method for calibrating an oscillation frequency of a controllable oscillator are provided. The FCAL circuit includes the controllable oscillator, a divider, a time-to-digital converter (TDC) and a calibration logic. The controllable oscillator generates a controllable oscillation clock according to a calibration code. The divider divides the oscillation frequency of the controllable oscillation clock by a predetermined divisor to generate a divided clock. The TDC converts a first period between first edges of a reference clock and the divided clock into a first period code and converts a second period between second edges of the reference clock and the divided clock into a second period code. The calibration logic compares the first period code and the second period code to generate a comparison result for determining whether the first period is greater or less than the second period, and accordingly controls the calibration code.

Abstract: A design of a test chip for determining the dopant uniformity of an ion implantation within a area of the order of several tens of microns is disclosed and a method for it's measurement provided. The object of the test chip is particularly adapted to sense dopant concentration variations caused by the variation of density in the spot of the ion implantation beam and can be used to determine optimal overlap of adjacent beam scans. The test chips use arrays of MOSFETs arranged in a pattern with channel lengths parallel to the path of the ion implantation beam and provide a contiguous set of incremental concentration measurements across the paths of the ion implantation beam scans. The gate threshold voltages are measured and related to the active dopant impurity concentration in the channel area. The width of the concentration increment is therefore equal to the channel length.

Abstract: A design of a test chip for determining the dopant uniformity of an ion implantation within a area of the order of several tens of microns is disclosed and a method for it's measurement provided. The object of the test chip is particularly adapted to sense dopant concentration variations caused by the variation of density in the spot of the ion implantation beam and can be used to determine optimal overlap of adjacent beam scans. The test chips use arrays of MOSFETs arranged in a pattern with channel lengths parallel to the path of the ion implantation beam and provide a contiguous set of incremental concentration measurements across the paths of the ion implantation beam scans. The gate threshold voltages are measured and related to the active dopant impurity concentration in the channel area. The width of the concentration increment is therefore equal to the channel length.

Abstract: A method for cleaning a semiconductor substrate. Introduced into a semiconductor substrate processing chamber is a semiconductor substrate. The semiconductor substrate and the semiconductor substrate processing chamber are maintained at a temperature not exceeding about 800 degrees centigrade. Introduced substantially simultaneously with the semiconductor substrate into the semiconductor substrate processing chamber is a low flow of a first oxidant gas. Introduced into the semiconductor substrate processing chamber immediately subsequent to the low flow of the first oxidant gas is a high flow of a second oxidant gas. Introduced into the semiconductor wafer processing chamber no earlier than the high flow of the second oxidant gas is a flow of a chlorine containing getter material.

Abstract: An improved method is described for planarizing dielectric layers which are formed between conductor layers in integrated circuits A three layer spin-on-glass sandwich is formed comprising a first silicon oxide layer, a spin-on-glass layer and a second silicon oxide layer. The improvement comprises performing an O.sub.2 plasma treatment on the first silicon oxide layer prior to forming the overlying spin-on-glass layer. The method prevents delamination (separation) between the first silicon oxide layer and the middle spin-on-glass layer.