Abstract: A speed-up charge pump includes a first charge pump for receiving an up signal and a down signal in digital form to produce a first voltage control signal at an output node. Further, at least one speed-up phase detector includes a first circuit path to receive the up signal and delay the up signal by a predetermined delay as a delay up signal and operate the up signal and the delay up signal by AND logic into an auxiliary up signal; and a second circuit path to receive the down signal and delay the down signal by the predetermined delay as a delay down signal and operate the down signal and the delay down signal by AND logic into an auxiliary down signal. A second charge pump is respectively receiving the auxiliary up and down signals to produce a second voltage control signal also at the output node.

Abstract: A multi-phase switched capacitor power converter and a control method thereof are disclosed. The multi-phase switched capacitor power converter includes a first phase converting circuit and a second phase converting circuit. The first phase converting circuit and the second phase converting circuit include switches and a flying capacitor respectively. The switches are coupled in series and there are a first node and a second node between the switches. The flying capacitor is coupled to the first node and the second node. When the first phase converting circuit is in an operating mode and the second phase converting circuit is in a standby mode, the control method controls a part of the switches in the second phase converting circuit continuously conducted to charge the flying capacitor.

Abstract: Provided is a manual centrifugal device, including a rotating platform disposed with a rotating shaft, and a plurality of blood storage tubes fixed to the rotating platform at a regular intervals, wherein the rotating platform and the plurality of blood storage tubes rotate relative to the plane of placement during centrifugation. Further provided is a method for separating blood. The centrifugal device is driven manually to centrifugally separate blood cells and blood plasma, thereby greatly reducing the medical cost of blood examination and providing a more convenient and simple blood separation method for the low-resource areas.

Abstract: The present invention provides a layout of a semiconductor transistor device including a first and a second active area, a first and a second gate, and a metal line. The first active and the second active area are extended along a first direction. The first gate and the second gate are extended along a second direction and crossed the first active area, to define two transistors. The two transistors are electrically connected with each other through a conductive layer. The metal line is disposed on the conductive layer and is electrically connected the two transistors respectively.

Abstract: The invention provides a testkey detection circuit, including a plurality of oscillators and a driving circuit. Each of the oscillators has an enable terminal, a voltage terminal and an output terminal, wherein the enable terminals are connected to a common enable terminal. The driving circuit receives the output terminals of the oscillators and increases a driving level of a selected one of the output terminals as a frequency output.

Abstract: The present disclosure provides a paper-based vertical flow test platform including: a detection portion; a movable conjugation portion having an enzyme-labelled protein; and an absorbent portion. The present disclosure further provides a detection method by using the same. With the folding and sliding design, the present disclosure can reduce the volume of specimen fluids used, and prevent the interference problem. Also, a portable diagnostic test platform is provided with ease of use, lower cost, higher sensitivity and longer storage period to meet requirements of point-of-care for the fast, simple and stable detection.

Abstract: A post and deck combination for a shelf assembly includes a hollow vertical post having an outer wall with slots at different heights. Each slot has a positioning portion. A coupling board is disposed on an edge of a deck and includes a first insertion groove. A coupling member includes a columnar portion interconnected between first and second ends thereof and having a first section with a diameter smaller than a width of each positioning portion and a second section received in the first insertion groove. The coupling member extends through one of the slots. The positioning portion of the one of the slots is located at the first section. The first insertion groove is coupled with the first end of the coupling member. A first receiving end of the first insertion groove is located on an inclined guiding face of the second section.

Abstract: A detection device adapted for detecting an analyte in a sample includes a substrate having a top surface, a sample pad, a binding pad, a cellulose pad, a nitrocellulose membrane and an absorbent pad. The sample pad is for receiving the sample. The binding pad includes a main body and a first detecting reagent disposed on the main body and is adapted for specifically binding to the analyte. The cellulose pad has a first connecting end portion and a second connecting end portion. The nitrocellulose membrane includes a membrane body and a detection zone that includes a second detecting reagent adapted for specifically binding to the analyte. The absorbent pad connects to the membrane body.

Abstract: The present invention provides an integrated circuit with a standard cell of an inverter standard cell. The integrated circuit includes: a first metal line and a second metal line stretching along a first direction; a first dummy gate and a second dummy gate stretching along a second direction; Plural fin structures stretching along the first direction; A gate structure disposed on the fin structures and stretching along the second direction; Two long contact plugs disposed at one side of the gate structure; two short contact plugs disposed at the other side of the gate structure; a gate contact plug disposed on the gate structure; Plural via plugs disposed on the long contact plugs, the short contact plugs and the gate contact plugs; A metal layer includes the first metal line, the second metal line, a third metal line and a fourth metal line.

Abstract: The present invention provides an integrated circuit with a standard cell of an inverter. The integrated circuit includes: a first metal line and a second metal line stretching along a first direction; a first dummy gate and a second dummy gate stretching along a second direction; Plural fin structures stretching along the first direction; A gate structure disposed on the fin structures and stretching along the second direction; Two long contact plugs disposed at one side of the gate structure; two short contact plugs disposed at the other side of the gate structure; a gate contact plug disposed on the gate structure; Plural via plugs disposed on the long contact plugs, the short contact plugs and the gate contact plugs; A metal layer includes the first metal line, the second metal line, a third metal line and a fourth metal line.

Abstract: The present invention provides an integrated circuit with a standard cell of an inverter. The integrated circuit includes: a first metal line and a second metal line stretching along a first direction; a first dummy gate and a second dummy gate stretching along a second direction; Plural fin structures stretching along the first direction; A gate structure disposed on the fin structures and stretching along the second direction; Two long contact plugs disposed at one side of the gate structure; two short contact plugs disposed at the other side of the gate structure; a gate contact plug disposed on the gate structure; Plural via plugs disposed on the long contact plugs, the short contact plugs and the gate contact plugs; A metal layer includes the first metal line, the second metal line, a third metal line and a fourth metal line.

Abstract: The present invention provides an integrated circuit with a standard cell of an inverter standard cell. The integrated circuit includes: a first metal line and a second metal line stretching along a first direction; a first dummy gate and a second dummy gate stretching along a second direction; Plural fin structures stretching along the first direction; A gate structure disposed on the fin structures and stretching along the second direction; Two long contact plugs disposed at one side of the gate structure; two short contact plugs disposed at the other side of the gate structure; a gate contact plug disposed on the gate structure; Plural via plugs disposed on the long contact plugs, the short contact plugs and the gate contact plugs; A metal layer includes the first metal line, the second metal line, a third metal line and a fourth metal line.

Abstract: The present invention provides an integrated circuit with a dummy standard cell. The integrated circuit includes: a first metal line and a second metal line stretching along a first direction; a first dummy gate and a second dummy gate stretching along a second direction; Plural fin structures stretching along the first direction; A gate structure disposed on the fin structures and stretching along the second direction; Plural sets of short contact plug and long contact plug disposed between the first dummy gate, the second dummy gate and the gate structures; a doping region overlaps with the long contact plugs; a gate contact plug disposed on the gate structures; plural contact plugs disposed on and electrical contact the long contact plugs; A metal layer includes the first metal line, the second metal line.

Abstract: The present invention provides a layout of a semiconductor transistor device including a first and a second active area, a first and a second gate, and a metal line. The first active and the second active area are extended along a first direction. The first gate and the second gate are extended along a second direction and crossed the first active area, to define two transistors. The two transistors are electrically connected with each other through a conductive layer. The metal line is disposed on the conductive layer and is electrically connected the two transistors respectively.

Abstract: A method for designing a semiconductor layout structure includes following steps. A first active feature group including at least a first active feature is received, and the first active feature includes a first channel length. A pair of first dummy features is introduced to form a first cell pattern. The first dummy features include a first dummy width. A first spacing width is defined between the first active feature group and one of the first dummy features and a third spacing width is defined between the first active feature group and the other first dummy feature. The first cell pattern includes a first cell width and a first poly pitch, and the first cell width is a multiple of the first pitch. The receiving of the first active feature group and the introducing of the first dummy features are performed in by at least a computer-aided design tool.

Abstract: A shelf assembly includes four vertical posts each having vertically spaced first engaging holes and vertically spaced second engaging holes. Each of two horizontal beams includes a first board. Each end of each horizontal beam includes a third engaging groove and a first buckle having a first coupling groove. Each of two connecting beams includes a second board. Each end of the second board includes a second buckle having a second coupling groove. A support board is mounted on top of the horizontal beams and the connecting beams. Each first buckle engages one of the first engaging holes. Each second buckle extends through one of the third engaging holes and one of the second engaging holes. Each first coupling groove engages a bottom edge of one of the first engaging holes. Each second coupling groove securely receives a corresponding connecting wall and the first board of a corresponding horizontal beam.

Abstract: An electronic device is provided, including a housing having a side wall, a display panel, a push latch, a video/audio transceiver, and an elastic member, wherein the display panel is disposed in the housing. The push latch is fixed on the housing. The video/audio transceiver is movably disposed in the housing, and has a connecting portion. The elastic member connects the video/audio transceiver with the housing. When the connecting portion is connected to the push latch, the video/audio transceiver is in a first position. When the connecting portion is separated from the push latch, the video/audio transceiver moves from the first position to a second position and protrudes from the side wall due to the elastic force of the elastic member.

Abstract: A 6T static random access memory cell, array, and memory thereof are provided, in which the memory cell includes a first inverter, a second inverter, a first NMOS transistor, and a second NMOS transistor. A first high supply voltage and a low supply voltage are coupled to the first inverter. A second high supply voltage and the low supply voltage are coupled to the second inverter. The first NMOS transistor has a gate terminal coupled to a first word line. The first NMOS transistor has a source terminal coupled to the first node. The second NMOS transistor has a gate terminal coupled to a second word line, and the second NMOS transistor has a source terminal coupled to the second node. The first word line provides ON signals to turn on the first NMOS transistor, and the second high supply voltage provides a first boost voltage simultaneously.

Abstract: A method for designing a semiconductor layout structure includes following steps. A first active feature group including at least a first active feature is received, and the first active feature includes a first channel length. A pair of first dummy features is introduced to form a first cell pattern. The first dummy features include a first dummy width. A first spacing width is defined between the first active feature group and one of the first dummy features and a third spacing width is defined between the first active feature group and the other first dummy feature. The first cell pattern includes a first cell width and a first poly pitch, and the first cell width is a multiple of the first pitch. The receiving of the first active feature group and the introducing of the first dummy features are performed in by at least a computer-aided design tool.

Abstract: A ternary content-addressable memory comprises a first switch, a first static random-access memory cell, a second switch and a second static random-access memory cell. The first switch is connected between a first search line and a match line. The first switch has a first control electrode. The first static random-access memory cell has a first storage node connected to the first control electrode of the first switch. The second switch is connected between a second search line and the match line. The second switch has a second control node. The second static random-access memory cell has a second storage node connected to the second control electrode of the second switch.