Patents by Inventor Chien-Fu Tseng

Chien-Fu Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150113353
    Abstract: A decoding method, a memory storage device, a memory controlling circuit unit and a decoding circuit for low density parity code (LDPC) are provided. The decoding method includes: reading a data bit of each memory cell; performing a parity check procedure on the data bits to generate a plurality of checks; in an iterative decoding of LDPC, obtaining a reliability message of each data bit according to the checks and deciding an index of an error bit from the data bits according to the reliability messages; determining whether the index of the error bit and the checks comply with a parity criteria; and if the index of the error bit and the checks comply with the parity criteria, stopping the iterative decoding and outputting the index of the error bit. Accordingly, a decoding latency is decreased.
    Type: Application
    Filed: January 1, 2014
    Publication date: April 23, 2015
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chien-Fu Tseng
  • Patent number: 8832526
    Abstract: A data reading method adapted to a rewritable non-volatility memory module having physical blocks is provided, wherein each physical block has a plurality of physical pages. In the data reading method, each physical page is partitioned into bit data areas, where at least one of the bit data areas has a data length different from that of the other bit data areas. Data is written into the bit data areas. Data in each bit data area is corresponding to an ECC frame. The data is read from the bit data areas. Because the at least one of bit data areas has a relatively short data length, the error correction capability is improved and the data can be correctly read. An error bit information is obtained according to the read data. A log likelihood ratio (LLR) lookup table or a threshold voltage is adjusted according to the error bit information.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: September 9, 2014
    Assignee: Phison Electronics Corp.
    Inventors: Chien-Fu Tseng, Kuo-Hsin Lai
  • Publication number: 20140133225
    Abstract: A data compensating method for a flash memory is provided. Firstly, a first threshold voltage distribution curve of the cells of the flash memory with a first storing state is acquired. Then, a second threshold voltage distribution curve of the cells of the flash memory with a second storing state is acquired. Then, a first occurrence probability of a first type ICI pattern of the first storing state is calculated according to a statistic voltage range and the first threshold voltage distribution curve. A second occurrence probability of the first type ICI pattern of the second storing state is acquired according to the statistic voltage range and the second threshold voltage distribution curve. During a read cycle, storing states of central cells corresponding to the first type ICI pattern are compensated according to the first occurrence probability and the second occurrence probability.
    Type: Application
    Filed: December 27, 2012
    Publication date: May 15, 2014
    Applicant: LITE-ON IT CORPORATION
    Inventors: Shih-Jia Zeng, Chien-Fu Tseng, Hsie-Chia Chang, Yen-Yu Chou
  • Publication number: 20140136924
    Abstract: A method for determining a storing state of a flash memory is provided. The method includes the following steps. Firstly, plural first specific cell patterns are programmed into the flash memory. Then, plural second specific cell patterns are programmed into the flash memory. Then, a slicing voltage is adjusted to allow a distinguishable error percentage to be lower than a predetermined value. Afterwards, a first storing state and a second storing state of other cells of the flash memory are distinguished from each other according to the adjusted slicing voltage.
    Type: Application
    Filed: March 21, 2013
    Publication date: May 15, 2014
    Applicant: LITE-ON IT CORPORATION
    Inventors: Shih-Jia Zeng, Chien-Fu Tseng, Hsie-Chia Chang, Yen-Yu Chou
  • Patent number: 8578245
    Abstract: A data reading method for a rewritable non-volatile memory module is provided, wherein the rewritable non-volatile memory module has a plurality of physical pages. The data reading method includes grouping the physical pages into a plurality of physical page groups and configuring a corresponding threshold voltage set for each of the physical page groups. The data reading method also includes respectively reading data from the physical pages of the physical page groups by using the corresponding threshold voltage sets. The data reading method further includes when data read from one of the physical pages of one of the physical page groups cannot be corrected by using an error checking and correcting (ECC) circuit, updating the threshold voltage set corresponding to the physical page group.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: November 5, 2013
    Assignee: Phison Electronics Corp.
    Inventors: Chih-Kang Yeh, Chien-Fu Tseng, Chung-Lin Wu
  • Patent number: 8510637
    Abstract: A data reading method for a writable non-volatile memory module having physical pages is provided. The method includes grouping the physical pages into a plurality of physical page groups. The method also includes reading first data from a physical page of a first physical page group by applying a first threshold voltage set. The method still includes, when the first data can be corrected by an error checking and correcting circuit and an error bit number corresponding to the first data is not smaller than an error bit number threshold, calculating compensation voltages for the first threshold voltage set. The method further includes adjusting the first threshold voltage set by the compensation voltages and applying the adjusted first threshold voltage set to read data from the physical pages of the first physical page group. Accordingly, data stored in the rewritable non-volatile memory module can be correctly read.
    Type: Grant
    Filed: May 16, 2011
    Date of Patent: August 13, 2013
    Assignee: Phison Electronics Corp.
    Inventors: Chien-Fu Tseng, Kuo-Hsin Lai
  • Patent number: 8429501
    Abstract: A memory storage device, a memory controller, and a log likelihood ratio (LLR) generation method are provided. A read data corresponding to a first storage state is obtained from memory cells of a flash memory chip in the memory storage device by using bit data read voltages. An error checking and correcting procedure is performed on the read data to obtain a second storage state corresponding to the read data when the read data is written. An amount of storage error is obtained in storage states satisfying a statistic number, and a storage error means that data is in the second storage state when being written and is in the first storage state when being read. A logarithmic operation is executed according to the statistic number, an amount of the storage states, and the amount of storage error to generate a first LLR of the read data.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: April 23, 2013
    Assignee: Phison Electronics Corp.
    Inventors: Chien-Fu Tseng, Kuo-Hsin Lai
  • Patent number: 8386860
    Abstract: Methods of calculating a compensation voltage and adjusting a threshold voltage, a memory apparatus, and a controller are provided. In the present invention, data is written into a rewritable non-volatility memory, and the data is then read from the rewritable non-volatility memory and compared with the previously written data to obtain error bit information. The compensation voltage of the threshold voltage is calculated according to the error bit information, and the threshold voltage is adjusted according to the compensation voltage.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: February 26, 2013
    Assignee: Phison Electronics Corp.
    Inventors: Chien-Fu Tseng, Kuo-Hsin Lai, Li-Chun Liang
  • Publication number: 20120311402
    Abstract: A data reading method adapted to a rewritable non-volatility memory module having physical blocks is provided, wherein each physical block has a plurality of physical pages. In the data reading method, each physical page is partitioned into bit data areas, where at least one of the bit data areas has a data length different from that of the other bit data areas. Data is written into the bit data areas. Data in each bit data area is corresponding to an ECC frame. The data is read from the bit data areas. Because the at least one of bit data areas has a relatively short data length, the error correction capability is improved and the data can be correctly read. An error bit information is obtained according to the read data. A log likelihood ratio (LLR) lookup table or a threshold voltage is adjusted according to the error bit information.
    Type: Application
    Filed: July 26, 2011
    Publication date: December 6, 2012
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Chien-Fu Tseng, Kuo-Hsin Lai
  • Patent number: 8289771
    Abstract: A data reading method for a flash memory module is provided. The method includes applying a bit-data-read voltage to get read data from memory cells of the flash memory module. The method also includes setting a minus-adjustment-bit-data-read voltage and a plus-adjustment-bit-data-read voltage corresponding to the bit-data-read voltage based on an error-distribution estimated value and applying the minus-adjustment-bit-data-read voltage and the plus-adjustment-bit-data-read voltage to obtain soft values corresponding to the read data from the memory cells. The method further includes calculating a soft-information estimated value corresponding to each bit of the read data according to the soft-values. Accordingly, the method can effectively obtain soft information.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: October 16, 2012
    Assignee: Phison Electronics Corp.
    Inventors: Chien-Fu Tseng, Kuo-Hsin Lai
  • Patent number: 8276033
    Abstract: A data writing method for a flash memory, and a flash memory controller and a flash memory storage apparatus using the same are provided. First, data is received from a host system. Next, the data is divided into at least one frame. Afterwards, an error checking and correcting (ECC) code corresponding to the frame is generated so as to form at least one ECC frame. Then, the ECC frame is divided into a plurality of frame segments. Finally, the frame segments are written into a flash memory chip according to a non-sequentially ranking order.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: September 25, 2012
    Assignee: Phison Electronics Corp.
    Inventors: Chien-Fu Tseng, Yu-Hung Liu, Li-Chun Liang, Chih-Kang Yeh
  • Publication number: 20120144267
    Abstract: A data reading method for a rewritable non-volatile memory module is provided, wherein the rewritable non-volatile memory module has a plurality of physical pages. The data reading method includes grouping the physical pages into a plurality of physical page groups and configuring a corresponding threshold voltage set for each of the physical page groups. The data reading method also includes respectively reading data from the physical pages of the physical page groups by using the corresponding threshold voltage sets. The data reading method further includes when data read from one of the physical pages of one of the physical page groups cannot be corrected by using an error checking and correcting (ECC) circuit, updating the threshold voltage set corresponding to the physical page group.
    Type: Application
    Filed: March 1, 2011
    Publication date: June 7, 2012
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Chih-Kang Yeh, Chien-Fu Tseng, Chung-Lin Wu
  • Patent number: 8154974
    Abstract: A holographic data storing method includes the steps of: encoding original data to generate holographic data according to a codeword to symbol relation; and recording a hologram corresponding to the holographic data onto a holographic storage medium. In the codeword to symbol relation, a plurality of sample symbols corresponds to a plurality of codewords. Each of the sample symbols corresponds to a pattern having N*N pixels. There are M bright pixels in the N*N pixels, wherein N and M are positive integers and M is smaller than N*N. A hamming distance of the sample symbols is greater than or equal to 4, and a two-dimensional run-length of the sample symbols is greater than or equal to 2.
    Type: Grant
    Filed: March 10, 2009
    Date of Patent: April 10, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Chien-Fu Tseng, Po-Chang Chen, Feng-Hsiang Lo, Jenn-Hwan Tarng
  • Publication number: 20120072805
    Abstract: A memory storage device, a memory controller, and a log likelihood ratio (LLR) generation method are provided. A read data corresponding to a first storage state is obtained from memory cells of a flash memory chip in the memory storage device by using bit data read voltages. An error checking and correcting procedure is performed on the read data to obtain a second storage state corresponding to the read data when the read data is written. An amount of storage error is obtained in storage states satisfying a statistic number, and a storage error means that data is in the second storage state when being written and is in the first storage state when being read. A logarithmic operation is executed according to the statistic number, an amount of the storage states, and the amount of storage error to generate a first LLR of the read data.
    Type: Application
    Filed: November 16, 2010
    Publication date: March 22, 2012
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Chien-Fu Tseng, Kuo-Hsin Lai
  • Publication number: 20110317488
    Abstract: A data reading method for a flash memory module is provided. The method includes applying a bit-data-read voltage to get read data from memory cells of the flash memory module. The method also includes setting a minus-adjustment-bit-data-read voltage and a plus-adjustment-bit-data-read voltage corresponding to the bit-data-read voltage based on an error-distribution estimated value and applying the minus-adjustment-bit-data-read voltage and the plus-adjustment-bit-data-read voltage to obtain soft values corresponding to the read data from the memory cells. The method further includes calculating a soft-information estimated value corresponding to each bit of the read data according to the soft-values. Accordingly, the method can effectively obtain soft information.
    Type: Application
    Filed: August 23, 2010
    Publication date: December 29, 2011
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Chien-Fu Tseng, Kuo-Hsin Lai
  • Publication number: 20110281136
    Abstract: A copper-manganese bonding structure adopted for use on Under Bump Metallurgy (UBM) at solder joints in packaging technology includes an electronic element, at least one soldering material and at least one manganese bonding material. The electronic element has at least one copper conductive portion. The soldering material corresponds to the copper conductive portion. The manganese bonding material is arranged in the copper conductive portion and the soldering material to form bonding between them. The manganese bonding material can reduce the generation of a brittle intermetallic compound Cu3Sn and suppress the generation of voids. The copper conductive portion is not consumed by the generation of the intermetallic compound. Thus the total structure can be protected and improved.
    Type: Application
    Filed: May 14, 2010
    Publication date: November 17, 2011
    Inventors: Jenq-Gong Duh, Chien-Fu Tseng
  • Publication number: 20110258495
    Abstract: Methods of calculating a compensation voltage and adjusting a threshold voltage, a memory apparatus, and a controller are provided. In the present invention, data is written into a rewritable non-volatility memory, and the data is then read from the rewritable non-volatility memory and compared with the previously written data to obtain error bit information. The compensation voltage of the threshold voltage is calculated according to the error bit information, and the threshold voltage is adjusted according to the compensation voltage.
    Type: Application
    Filed: May 27, 2010
    Publication date: October 20, 2011
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Chien-Fu Tseng, Kuo-Hsin Lai, Li-Chun Liang
  • Publication number: 20110258496
    Abstract: A data reading method for a writable non-volatile memory module having physical pages is provided. The method includes grouping the physical pages into a plurality of physical page groups. The method also includes reading first data from a physical page of a first physical page group by applying a first threshold voltage set. The method still includes, when the first data can be corrected by an error checking and correcting circuit and an error bit number corresponding to the first data is not smaller than an error bit number threshold, calculating compensation voltages for the first threshold voltage set. The method further includes adjusting the first threshold voltage set by the compensation voltages and applying the adjusted first threshold voltage set to read data from the physical pages of the first physical page group. Accordingly, data stored in the rewritable non-volatile memory module can be correctly read.
    Type: Application
    Filed: May 16, 2011
    Publication date: October 20, 2011
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Chien-Fu Tseng, Kuo-Hsin Lai
  • Publication number: 20110154162
    Abstract: A data writing method for a flash memory, and a flash memory controller and a flash memory storage apparatus using the same are provided. First, data is received from a host system. Next, the data is divided into at least one frame. Afterwards, an error checking and correcting (ECC) code corresponding to the frame is generated so as to form at least one ECC frame. Then, the ECC frame is divided into a plurality of frame segments. Finally, the frame segments are written into a flash memory chip according to a non-sequentially ranking order.
    Type: Application
    Filed: February 12, 2010
    Publication date: June 23, 2011
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Chien-Fu Tseng, Yu-Hung Liu, Li-Chun Liang, Chih-Kang Yeh
  • Patent number: 7957045
    Abstract: A hologram media reading apparatus including a reference light source, a stop with gray level aperture, and an optical sensor is provided. The reference light source is disposed on one side of a hologram medium, and capable of emitting a reference light beam. The reference light beam is transmitted to the hologram medium. The stop with gray level aperture and the reference light source are disposed on the same side or opposite sides of the hologram medium. The stop with gray level aperture has a light transmissive region, an opaque region, and a transmittance gradually varying region. The opaque region surrounds the light transmissive region. The transmittance gradually varying region surrounds the light transmissive region. A part of the reference beam from the hologram medium passes through the stop with gray level aperture and is transmitted to the optical sensor.
    Type: Grant
    Filed: September 16, 2008
    Date of Patent: June 7, 2011
    Assignee: Industrial Technology Research Institute
    Inventors: Chien-Fu Tseng, Feng-Hsiang Lo, Jenn-Hwan Tarng, Chih-Ming Lin