Abstract: An antenna module including a first radiator and a second radiator is provided. The first radiator includes a first segment to a fifth segment connected in sequence. A first slot is formed between the second segment and the fourth segment. The second radiator has an edge. A first retracting distance is between the second segment and an extension line. A second retracting distance is between the fourth segment and the extension line. The first segment resonates at a first high frequency band. The first radiator and the first slot resonate at a low frequency band and a second high frequency band. The first retracting distance, the second retracting distance, the second segment, the fourth segment, the fifth segment and the first slot resonate at a third high frequency band. The first segment and the second radiator resonate at a fourth high frequency band. In addition, an electronic device is provided.

Abstract: An embodiment system, configured to clean a semiconductor package assembly, may include a sprayer device including a plurality of nozzles configured to direct a pressurized cleaning fluid toward the semiconductor package assembly; a conveyor configured to move the semiconductor package assembly relative to the sprayer device along a first direction; and a dryer spatially displaced from the sprayer device and configured to direct a pressurized gas flow toward the semiconductor package assembly to remove cleaning fluid introduced by the sprayer device. Each of the plurality of nozzles may be displaced from one another along a second direction to thereby generate respective separate spray distribution patterns. Adjacent nozzles may be further displaced from one another along a third direction to thereby a reduce an overlap of adjacent spray distribution patterns relative to a configuration in which the adjacent nozzles are not displaced from one another along the third direction.

Abstract: In some embodiments, the present disclosure relates to a semiconductor device comprising a source and drain region arranged within a substrate. A conductive gate is disposed over a doped region of the substrate. A gate dielectric layer is disposed between the source region and the drain region and separates the conductive gate from the doped region. A bottommost surface of the gate dielectric layer is below a topmost surface of the substrate. First and second sidewall spacers are arranged along first and second sides of the conductive gate, respectively. An inner portion of the first sidewall spacer and an inner portion of the second sidewall spacer respectively cover a first and second top surface of the gate dielectric layer. A drain extension region and a source extension region respectively separate the drain region and the source region from the gate dielectric layer.

Abstract: In some embodiments, the present disclosure relates to a semiconductor device comprising a source and drain region arranged within a substrate. A conductive gate is disposed over a doped region of the substrate. A gate dielectric layer is disposed between the source region and the drain region and separates the conductive gate from the doped region. A bottommost surface of the gate dielectric layer is below a topmost surface of the substrate. First and second sidewall spacers are arranged along first and second sides of the conductive gate, respectively. An inner portion of the first sidewall spacer and an inner portion of the second sidewall spacer respectively cover a first and second top surface of the gate dielectric layer. A drain extension region and a source extension region respectively separate the drain region and the source region from the gate dielectric layer.

Abstract: An electronic device includes a metal back cover, a metal frame, a first antenna module and a second antenna module. The metal frame includes a first and a second disconnection portion, a first and a second connection portion. The first and the second connection portion are connected to the metal back cover. The first disconnection portion is separated from the first connection portion, the metal back cover and the second disconnection portion to form a first slot. The second disconnection portion is connected to the second connection portion and is separated from the metal back cover to form a second slot. The first antenna module is connected to the first disconnection portion, and forms a first antenna path. The second antenna module is connected to the second disconnection portion, and forms a second and a third antenna path with the second disconnection portion and the metal back cover.

Abstract: A method includes forming a dielectric layer over a substrate; forming a carbon nanotube (CNT) over the dielectric layer; forming a dummy gate structure over the CNT; forming gate spacers on opposite sidewalls of the dummy gate structure; forming source/drain epitaxy structures on opposite sides of the dummy gate structure and in contact with opposite sidewalls of the CNT; replacing the dummy gate structure with a metal gate structure; and forming source/drain contacts over the source/drain epitaxy structures, respectively.

Abstract: Semiconductor devices and methods of forming the same are provided. A method includes providing a workpiece having a semiconductor structure; depositing a two-dimensional (2D) material layer over the semiconductor structure; forming a source feature and a drain feature electrically connected to the semiconductor structure and the 2D material layer, wherein the source feature and drain feature include a semiconductor material; and forming a gate structure over the two-dimensional material layer and interposed between the source feature and the drain feature. The gate structure, the source feature, the drain feature, the semiconductor structure and the 2D material layer are configured to form a field-effect transistor. The semiconductor structure and the 2D material layer function, respectively, as a first channel and a second channel between the source feature and the drain feature.

Abstract: A semiconductor device includes a channel having a first linear surface and a first non-linear surface. The first non-linear surface defines a first external angle of about 80 degrees to about 100 degrees and a second external angle of about 80 degrees to about 100 degrees. The semiconductor device includes a dielectric region covering the channel between a source region and a drain region. The semiconductor device includes a gate electrode covering the dielectric region between the source region and the drain region.

Abstract: A semiconductor device includes a first channel having a first linear surface and a first non-linear surface. The semiconductor device includes a first dielectric region surrounding the first channel. The semiconductor device includes a second channel having a third linear surface and a third non-linear surface. The semiconductor device includes a second dielectric region surrounding the second channel. The semiconductor device includes a gate electrode surrounding the first dielectric region and the second dielectric region.

Abstract: A semiconductor device includes a first channel having a first linear surface and a first non-linear surface. The semiconductor device includes a first dielectric region surrounding the first channel. The semiconductor device includes a second channel having a third linear surface and a third non-linear surface. The semiconductor device includes a second dielectric region surrounding the second channel. The semiconductor device includes a gate electrode surrounding the first dielectric region and the second dielectric region.

Abstract: A semiconductor device includes a channel having a first linear surface and a first non-linear surface. The first non-linear surface defines a first external angle of about 80 degrees to about 100 degrees and a second external angle of about 80 degrees to about 100 degrees. The semiconductor device includes a dielectric region covering the channel between a source region and a drain region. The semiconductor device includes a gate electrode covering the dielectric region between the source region and the drain region.

Abstract: A semiconductor device includes a first channel having a first linear surface and a first non-linear surface. The semiconductor device includes a first dielectric region surrounding the first channel. The semiconductor device includes a second channel having a third linear surface and a third non-linear surface. The semiconductor device includes a second dielectric region surrounding the second channel. The semiconductor device includes a gate electrode surrounding the first dielectric region and the second dielectric region.

Abstract: A semiconductor device includes a channel having a first linear surface and a first non-linear surface. The first non-linear surface defines a first external angle of about 80 degrees to about 100 degrees and a second external angle of about 80 degrees to about 100 degrees. The semiconductor device includes a dielectric region covering the channel between a source region and a drain region. The semiconductor device includes a gate electrode covering the dielectric region between the source region and the drain region.

Abstract: A controlling module controls illuminant state of an illuminant module according to a controlling signal sent form a wireless controller. The controlling module is electrically connected to the illuminant module and includes a microprocessor, a wireless receiver, a regulator, and a driving unit. The wireless receiver is electrically connected to the microprocessor and receives the controlling signal sent form the wireless controller. The regulator is electrically connected to the microprocessor. The driving unit is electrically connected to the microprocessor and the illuminant module.

Abstract: A semiconductor device includes a first channel having a first linear surface and a first non-linear surface. The semiconductor device includes a first dielectric region surrounding the first channel. The semiconductor device includes a second channel having a third linear surface and a third non-linear surface. The semiconductor device includes a second dielectric region surrounding the second channel. The semiconductor device includes a gate electrode surrounding the first dielectric region and the second dielectric region.

Abstract: A semiconductor device includes a channel having a first linear surface and a first non-linear surface. The first non-linear surface defines a first external angle of about 80 degrees to about 100 degrees and a second external angle of about 80 degrees to about 100 degrees. The semiconductor device includes a dielectric region covering the channel between a source region and a drain region. The semiconductor device includes a gate electrode covering the dielectric region between the source region and the drain region.

Abstract: A liquid crystal (LC) display panel including a lower substrate with pixel structures, an upper substrate, and an LC layer is provided. Each of the pixel structures includes a transistor and a pixel electrode. The pixel electrode includes first and second pixel electrodes insulated from each other, respectively including a first pattern and a second pattern that different and complementary to each other. Each of the first pixel electrode and the second pixel electrode has at least a trunk with a width smaller than or equal to 10 microns and a plurality of branches. The LC layer is positioned between the upper and the lower substrates and includes a plurality of LC molecules and a plurality of polymers, which are formed on surfaces of at least one of the upper and the lower substrates to cause the plurality of LC molecules to have a pretilt angle.

Abstract: In an embodiment of the invention, a liquid crystal display is provided. The liquid crystal display includes a first substrate, a first electrode formed on the first substrate, wherein the first electrode includes a plurality of subpixels, and each the subpixel includes a plurality of subunits, and each the subunit includes a plurality of first slits and a plurality of second slits, wherein the first slits are connected to the second slits and the first slits of the subunits which are adjacent to each other are connected to each other, a second substrate opposite to the first substrate, a second electrode formed on the second substrate, and a liquid crystal layer disposed between the first electrode and the second electrode.

Abstract: A thin film transistor (TFT) substrate includes a substrate, data lines, scan lines and pixel electrodes. The data lines and the scan lines intersect each other on the substrate for defining pixel areas. The pixel electrodes are disposed in corresponding pixel areas. Each of the pixel electrodes defines at least two slits by which the pixel electrode is divided into at least two first areas and at least two second areas. The first areas and the second areas are insulated with respect to each other. The first areas are disposed diagonally and the second areas are disposed diagonally.

Abstract: A pixel array substrate and a liquid crystal display are provided. The liquid crystal display includes the pixel array substrate, an opposite substrate and a liquid crystal layer. The liquid crystal layer is disposed between the pixel array substrate and the opposite substrate. The pixel array substrate has plural pixel electrodes. Each pixel electrode has a first main portion, a second main portion, a plurality of first and second branches. The first main portion is substantially vertically connected to the second main portion and sequentially defines a first quadrant, a second quadrant, a third quadrant and a fourth quadrant. Each first branch is connected to the first main portion and/or the second main portion. The orientation angles of the first branches in the same quadrant are substantially identical. Each second branch is connected to a plurality of the first branches. Each quadrant has at least one of the second branches.