Abstract: A semiconductor chip includes a first intellectual property block. There are a second intellectual property block and a third intellectual property block around the first intellectual property block. There is a multiple metal layer stack over the first intellectual property block, the second intellectual property block, and the third intellectual property block. An interconnect structure is situated in the upper portion of the multiple metal layer stack. The interconnect structure is configured for connecting the first intellectual property block and the second intellectual property block. In addition, at least a part of the interconnect structure extends across and over the third intellectual property block.

Abstract: A successive thermal pyrolysis apparatus for waste rubber has a pyrolysis furnace unit and a steam heating unit. The pyrolysis furnace unit is a tube chain type pyrolysis furnace and substantially has conveyor tubes and a chain disc conveyor mounted through the conveyor tubes for conveying waste rubber along the conveyor tubes. The steam heating unit encloses a segment of the conveyor tubes and has multiple baffles mounted therein to form a tortuous flowing path for steam passing through to heat the pyrolysis furnace unit. The successive thermal pyrolysis apparatus can prevent the carbonized fragments from sticking to and blocking inner surfaces of the conveyor tubes. The waste rubber fragments are successively thermally decomposed while being conveyed through the conveyor tubes.

Abstract: A wireless communication method and device are provided. The wireless communication system includes a communication interface, a transmitter and a receiver. The communication interface includes a plurality of lanes. The transmitter is coupled to the communication interface. The transmitter segments a plurality of input data into a plurality of packets of the same length, and transmits the packets with packet-based transmission through the plurality of lanes. The receiver is coupled to the communication interface and receives the packets from the plurality of lanes.

Abstract: A multi-level replication counter storage device for multicast packet processing includes a first-level storage device and a second-level storage device. The first-level storage device stores a plurality of first count values associated with a same cell data of a first multicast packet required to be broadcasted to a plurality of multicast targets, wherein a sum of the stored first count values is equal to a number of multicast targets to which the same cell data of the first multicast packet is not broadcasted yet. The second-level storage device stores a second count value which is adjusted based on the first count values to indicate whether a multicast operation of the same cell data of the first multicast packet is accomplished.

Abstract: A packet processing apparatus includes a buffer manager (BM) circuit, an ingress drop queue manager (IDQM) circuit, and a queue manager (QM) circuit. The BM circuit maintains at least one multicast counter (MC) value for an ingress packet. The QM circuit maintains a plurality of egress queues for a plurality of egress ports, respectively. When the ingress packet is decided to be dropped for at least one egress port designated by the ingress packet, the QM circuit enqueues the ingress packet into the IDQM circuit without enqueuing the ingress packet into at least one egress queue of the at least one egress port, and the IDQM circuit refers to the ingress packet enqueued therein to request the BM circuit to perform cell release of the ingress packet.

Abstract: A link list processing apparatus has a storage device and a link list controller. The link list controller sets link list information, and writes the link list information into the storage device to create a link list in the storage device. The link list has a plurality of nodes each having a next node address field. The link list information includes a data pattern configured to indicate an end of the link list as well as auxiliary information. The link list controller stores the data pattern into the next node address field of a link-tail node of the link list.

Abstract: A link list processing apparatus has a storage device and a link list controller. The link list controller sets link list information, and writes the link list information into the storage device to create a link list in the storage device. The link list has a plurality of nodes each having a next node address field. The link list information includes a data pattern configured to indicate an end of the link list as well as auxiliary information. The link list controller stores the data pattern into the next node address field of a link-tail node of the link list.

Abstract: A multi-level replication counter storage device for multicast packet processing includes a first-level storage device and a second-level storage device. The first-level storage device stores a plurality of first count values associated with a same cell data of a first multicast packet required to be broadcasted to a plurality of multicast targets, wherein a sum of the stored first count values is equal to a number of multicast targets to which the same cell data of the first multicast packet is not broadcasted yet. The second-level storage device stores a second count value which is adjusted based on the first count values to indicate whether a multicast operation of the same cell data of the first multicast packet is accomplished.

Abstract: A switching fabric of a network device has a load dispatcher, a plurality of store units, a storage device, a plurality of fetch units, and a load assembler. Each of the store units is used to perform a write operation upon the storage device. Each of the fetch units is used to perform a read operation upon the storage device. The load dispatcher is used to dispatch ingress traffic to the store units, wherein a data rate between the load dispatcher and each of the store units is lower than a data rate of the ingress traffic. The load assembler is used to collect outputs of the fetch units to generate egress traffic, wherein a data rate between the load assembler and each of the fetch units is lower than a data rate of the egress traffic.

Abstract: High-speed networking application equipments with a layer-2 to layer-7 hardware search engine and method are with flexibility and performance improvement. The multi-layer switches/routers, network address translation (NAT) gateway, firewall/VPN router and network attached storage (NAS) may use the search engine for fast and efficient search requirement.

Abstract: High-speed networking application equipments with a layer-2 to layer-7 hardware search engine and method are with flexibility and performance improvement. The multi-layer switches/routers, network address translation (NAT) gateway, firewall/VPN router and network attached storage (NAS) may use the search engine for fast and efficient search requirement.

Abstract: High-speed networking application equipments with a layer-2 to layer-7 hardware search engine and method are with flexibility and performance improvement. The multi-layer switches/routers, network address translation (NAT) gateway, firewall/VPN router and network attached storage (NAS) may use the search engine for fast and efficient search requirement.

Abstract: An interrupt coalescing scheme for high throughput TCP offload engine and method thereof are disclosed. An interrupt descriptor queue is used, that TCP offload engine saves TCP connection information and interrupt information in an interrupt event descriptor per interrupt. Meanwhile the software processes an interrupt by reading interrupt event descriptors asynchronously. The software may process multiple interrupt event descriptors in one interrupt context.

Abstract: An exemplary thin film transistor (TFT) array substrate (200) includes: a substrate (210), a gate electrode (220) disposed on the substrate, a gate insulating layer (230) disposed on the substrate having the gate electrode, a lightly doped amorphous silicon (a-Si) layer (241) disposed on the gate insulating layer, a first a-Si layer (242) disposed on the lightly doped a-Si layer, a source electrode (251) and a drain electrode (252) disposed on the gate insulating layer and the a-Si layer. The thin film transistor array substrate has a low leakage current.

Abstract: High-speed networking application equipments with a layer-2 to layer-7 hardware search engine and method are with flexibility and performance improvement. The multi-layer switches/routers, network address translation (NAT) gateway, firewall/VPN router and network attached storage (NAS) may use the search engine for fast and efficient search requirement.