Abstract: An electronic device has a light emitting unit driving circuit. The driving circuit has a first driving transistor, a second driving transistor, and a light emitting unit. The first driving transistor has a first channel width and a first channel length and is used to provide a first current. The second driving transistor has a second channel width and a second channel length and is used to provide a second current. The light emitting unit is coupled to the first driving transistor and the second driving transistor for receiving at least one of the first current and the second current to emit light. A ratio of the first channel width to the first channel length is greater than a ratio of the second channel width to the second channel length.

Abstract: A display device includes a panel. The panel includes a display array and a first scan line group. The display array displays a first image and a second image following the first image, and has a first regulation array. The first scan line group is arranged corresponding to the first regulation array. There is a blanking period existed between a first update period corresponding to the first image and a second update period corresponding to the second image. The blanking period has a first sub-period. The first scan line group sends a first scan signal to the first regulation array in the first sub-period.

Abstract: An electronic device has a light emitting unit driving circuit. The driving circuit has a first driving transistor, a second driving transistor, and a light emitting unit. The first driving transistor has a first channel width and a first channel length and is used to provide a first current. The second driving transistor has a second channel width and a second channel length and is used to provide a second current. The light emitting unit is coupled to the first driving transistor and the second driving transistor for receiving at least one of the first current and the second current to emit light. A ratio of the first channel width to the first channel length is greater than a ratio of the second channel width to the second channel length.

Abstract: The invention provides a gate driving circuit for an in-cell touch panel to improve the issue wherein the undesired falling time of a pre-stage shift register and the undesired rising time of a next-stage shift register during a touch sensing period, in which the undesired falling time and the undesired rising time are caused by the output signal of the shift register cannot be correctly transmitted to the pre-stage shift register and the next-stage shift register during the touch sensing period.

Abstract: A display device includes a panel. The panel includes a display array and a first scan line group. The display array displays a first image and a second image following the first image, and has a first regulation array. The first scan line group is arranged corresponding to the first regulation array. There is a blanking period existed between a first update period corresponding to the first image and a second update period corresponding to the second image. The blanking period has a first sub-period. The first scan line group sends a first scan signal to the first regulation array in the first sub-period.

Abstract: A display panel includes a substrate, multiple data lines, multiple gate lines, a power line and a gate driver circuit. The power line is coupled to a power source. The gate driver circuit is disposed in an active area of the substrate and is coupled to the gate lines and the power line. The gate driver circuit generates multiple gate driving signals in response to a start pulse. The gate lines include a first metal layer disposed above the substrate. The data lines include a second metal layer disposed above the first metal layer. The power line includes a third metal layer disposed above the second metal layer. An orthogonal projection of at least one of the data lines onto the substrate overlaps an orthogonal projection of the power line onto the substrate.

Abstract: The invention provides a gate driving circuit for an in-cell touch panel to improve the issue wherein the undesired falling time of a pre-stage shift register and the undesired rising time of a next-stage shift register during a touch sensing period, in which the undesired falling time and the undesired rising time are caused by the output signal of the shift register cannot be correctly transmitted to the pre-stage shift register and the next-stage shift register during the touch sensing period.

Abstract: A gate driving circuit includes a plurality of shift registers connected in series. The shift registers include a plurality of output shift registers and X groups of dummy shift registers. The output shift registers output the gate driving signal to a plurality of gate driving lines of the pixel matrix in sequence. At least one of the X groups of dummy shift registers has J dummy shift registers and is connected between two adjacent output shift registers in the output shift registers, wherein at least one driving signal generated by the group of dummy shift registers is partially overlapped with the gate driving signal generated by the two adjacent output shift registers in a frame, wherein the X groups of dummy shift registers are not connected to the gate driving lines, and X and J are integers greater than zero.

Abstract: This disclosure provides a gate driver circuit in a display. The gate driver circuit includes shift registers configured for receiving clock and start signals and generating a gate signal to drive a row of the pixels, arranged at intersections of the gate lines and the data lines on a panel, each register comprising: a control unit having a clock input, a first voltage input, a second voltage input, and a first output; and a first output unit having a first pull-down TFT electrically connected to one of the first outputs and a gate-driving terminal configured for providing the gate signal; wherein one of the clock signals at the clock input is provided to the first output unit; and a first control signal's period at the first output is longer than the clock signal's period at the clock input and shorter than the period of a frame.

Abstract: A scan driving circuit of a display apparatus is electrically connected to the display panel through a plurality of scan lines and includes a plurality of stages of driving unit. The driving unit comprises a shift control device outputting a control signal according to a starting signal and a driving device. The driving device outputs an output signal to the corresponding scan line according to the control signal, a first trigger signal and a second trigger signal. The output signal is used as the starting signal of the next stage of driving unit, and the rising transition time of the second trigger signal and the falling transition time of the first trigger signal have an overlap.

Abstract: A gate line driving module used on a liquid crystal display uses clock signal sources in replacement of a high level gate power source, such that the phenomenon of device characteristic drift occurring in the foregoing related art is avoided. The gate line driving module includes a plurality of odd-pixel gate line driving circuits, a plurality of even-pixel gate line driving circuits, and an auxiliary gate line driving circuit. A pair of neighboring odd-pixel gate line driving circuit and even-pixel gate line driving circuit exchange output signals thereof with each other in a forward or feedback manner for ensuring that each the odd-pixel gate line driving circuit and each the even-pixel gate line driving circuit are driven once. The auxiliary gate line driving circuit is used for ensuring that signal iteration of the gate line driving module is under normal operation.

Abstract: A scan driving circuit of a display apparatus is electrically connected to the display panel through a plurality of scan lines and includes a plurality of stages of driving unit. The driving unit comprises a shift control device outputting a control signal according to a starting signal and a driving device. The driving device outputs an output signal to the corresponding scan line according to the control signal, a first trigger signal and a second trigger signal. The output signal is used as the starting signal of the next stage of driving unit, and the rising transition time of the second trigger signal and the falling transition time of the first trigger signal have an overlap.

Abstract: This disclosure provides a gate driver circuit in a display. The gate driver circuit includes shift registers configured for receiving clock and start signals and generating a gate signal to drive a row of the pixels, arranged at intersections of the gate lines and the data lines on a panel, each register comprising: a control unit having a clock input, a first voltage input, a second voltage input, and a first output; and a first output unit having a first pull-down TFT electrically connected to one of the first outputs and a gate-driving terminal configured for providing the gate signal; wherein one of the clock signals at the clock input is provided to the first output unit; and a first control signal's period at the first output is longer than the clock signal's period at the clock input and shorter than the period of a frame.

Abstract: A shift register includes first and second shift register units. Two adjacent first shift register units respectively receive a first and second clock signal. Two adjacent second shift register units respectively receive a third and a fourth clock signal. Each first and second shift register unit includes a cascade data input terminal, a cascade data output terminal, an output terminal used to output a shift signal, a feedback terminal, and a reset terminal. The shift signals of the Mth second and Nth first shift register unit are respectively fed back to the feedback terminal of the (N+1)th first and Mth second shift register unit. The reset terminal and the cascade data output terminal of the Nth first and Mth second shift register unit are respectively connected to the output terminal and the cascade data input terminal of (N+1)th first and (M+1)th second shift register unit.

Abstract: A shift register includes individually connected shift register units. Each shift register unit includes a switching unit, a pre-charging unit, a pulse signal output unit, a low level voltage signal control unit, a first clock pulse signal input, a second clock pulse signal input, and an output. The first and the second clock pulse signal inputs respectively receive a first clock signal and a second clock signal, the first clock signal and the second clock signal having reverse clock pulses during each clock cycle. The switching unit receives at least one external starting signal and a high level signal, when the at least one external starting signal is high level, the switching unit is turned on and outputs the high level signal to the pre-charging unit. When the second clock signal is high level, the pre-charging unit receives the high level signal and charges, and when the first clock signal is high level, the pre-charging unit discharges.

Abstract: The present invention relates to a shift register and a liquid crystal display using the same. The liquid crystal display includes a liquid crystal panel, a data driving circuit and a scanning driving circuit. The data driving circuit and the scanning driving circuit each include a shift register. The shift register includes a plurality of shift register units. Two adjacent shift register units respectively receive two inverse clock signals and a VGL signal. Each shift register unit includes a signal output circuit, a signal input circuit, a first logic converting circuit, and a second logic converting circuit. The present shift register and a liquid crystal display have simple structure.

Abstract: An exemplary shift register includes a plurality of shift register units, each of which includes an output circuit, an input circuit, and a logic circuit. The output circuit includes a clock transistor, a voltage stabilizing transistor, and an input circuit for receiving signals output by a previous shift register unit. The logic circuit receives signals output by the input circuit. When the input circuit outputs signals to switch on the clock transistor, the logic circuit outputs a low level voltage signal to shut off the voltage stabilizing transistor. Thus, the output circuit outputs signals via the clock circuit. On the other hand, when the input circuit outputs signals to shut off the clock transistor, the logic circuit outputs a high level voltage signal to turn on the voltage stabilizing transistor, so as to maintain the output circuit to output low level voltage signal.

Abstract: A shift register of the present disclosure comprises a plurality of shift register units using alternating clock signals to shift signals. The shift register outputs signals having substantially no overlap with adjacent signals. The shift register may be employed in a liquid crystal display.

Abstract: An exemplary shift register (20) includes a plurality of shift register units (200) connected one by one. Each of the shift register units includes a clock signal input terminal (TS), a high level signal input terminal (VH), a low level signal input terminal (VL), an output terminal (VOUT), a reverse output terminal (VOUTB), a first input terminal (VIN1), a second input terminal (VIN2), a first common node (P1), a second common node (P2), a first switch circuit (31), a second switch circuit (32), a third switch circuit (33), a fourth switch circuit (34), a fifth switch circuit (35), a six switch circuit (36), a first inverter (37) connected between the first common node and the second common node, and a second inverter (39) connected between the output terminal and the reverse output terminal.

Abstract: An exemplary shift register (20) includes a plurality of shift register units (200) connected one by one. Each of the shift register units includes a clock signal input terminal (TS), a high level signal input terminal (VH), a low level signal input terminal (VL), an input terminal (VIN), a first output terminal (VOUT1), a second output terminal (VOUT2), a first common node (P1), a second common node (P2), a first switch circuit (31), a second switch circuit (32), a third switch circuit (33), a fourth switch circuit (34), a fifth switch circuit (35), a six switch circuit (36), a nor gate, an inverter, and an and gate.