Abstract: Example implementations relate to computing device locations and computing devices having audio components thereon that change operational states. In some examples, a non-transitory computer-readable storage medium can include instructions that when executed cause a processor of an electronic device to determine a default host computing device of a plurality of computing devices, request a location of a first computing device of the plurality of computing devices using a sensor of the default host computing device, and request a location of a second computing device of the plurality of computing devices using the sensor. The instructions when executed can cause the processor to determine a first audio loop potential associated with the first computing device and a second audio loop potential associated with the second computing device, assign the first computing device as an active client and assign the second computing device as an inactive client.

Abstract: A landmark identification and marking system for a panoramic image is provided. The system includes a storage device and a back-end processor. The storage device stores an initial panoramic image, attitude information, motion tracking information, and a landmark list. The back-end processor performs steps of: adjusting a visual angle of the initial panoramic image to a designated angle according to a difference value between the visual angle and the designated angle; providing the adjusted initial panoramic image to a front-end processor for calculating and generating a panoramic image integrated with landmark objects in the virtual space.

Abstract: A method involves measuring, for an optical property of the display panel for an input gray level and at a first refresh rate, first and second values at respective first and second ambient brightness levels. The method also involves determining a compensation factor for the input gray level at the first refresh rate. The method further involves determining a modified gamma value at a second refresh rate, wherein the modified gamma value reduces a perceived optical defect of the display panel when operating at the second refresh rate by maintaining a consistent delta difference in values for the optical property between the first and second refresh rates at different ambient brightness levels. The method additionally involves storing the modified gamma value, where the device is configured to adjust input display data using the modified gamma value when transitioning from the first refresh rate to the second refresh rate.

Abstract: An electronic device includes a flexible substrate and a conductive wire. The conductive wire is disposed on the flexible substrate and includes a metal portion and a plurality of openings disposed in the metal portion. The metal portion includes a plurality of extending portions and a plurality of joint portions, and each of the openings is surrounded by two of the plurality of extending portions and two of the plurality of joint portions. A ratio of a sum of widths of the plurality of extending portions to a sum of widths of the plurality of joint portions is in a range from 0.8 to 1.2.

Abstract: A ship navigation display system is set in a ship and includes a communications device, sensing device, first computing device, second computing device and wearable device. The communications device receives first coordinate information corresponding to a ship. The sensing device senses second coordinate information corresponding to a first ship around the ship. The first computing device is communicably connected with the communications device and calculates a collision probability according to the first and second coordinate information. When the collision probability is greater than a threshold value, the first computing device transmits a collision prediction signal. The second computing device receives the collision prediction signal and projects the second coordinate information corresponding to the first ship to a virtual coordinate in a virtual space.

Abstract: A memory structure including a substrate, a first doped region, a second doped region, a first gate, a second gate, a first charge storage structure, and a second charge storage structure is provided. The first gate is located on the first doped region. The second gate is located on the second doped region. The first charge storage structure is located between the first gate and the first doped region. The first charge storage structure includes a first tunneling dielectric layer, a first dielectric layer, and a first charge storage layer. The second charge storage structure is located between the second gate and the second doped region. The second charge storage structure includes a second tunneling dielectric layer, a second dielectric layer, and a second charge storage layer. The thickness of the second tunneling dielectric layer is greater than the thickness of the first tunneling dielectric layer.

Abstract: A method for calibrating input display data for multiple display refresh rates comprises measuring (1210) an optical property of a display panel for an input gray level at a first refresh rate, measuring (1220) the optical property for a plurality of candidate gray levels at a second refresh rate, selecting (1230), based on the measured optical properties of the display panel, a corresponding gray level for the input gray level, wherein the corresponding gray level is selected from the plurality of candidate gray levels and storing (1240), at the device, the corresponding gray level for the input gray level, wherein subsequent to the storing, the device is configured to adjust input display data using the corresponding gray level for the input gray level when the display panel is transitioning from the first refresh rate to the second refresh rate.

Abstract: Devices and methods are described for reducing etching due to Galvanic Effect within a printed circuit board (PCB) that may be used in an electronic device. Specifically, a contact trace is coupled to a contact finger that has a substantially larger surface area than the contact trace. The contact finger is configured to couple the electronic device to a host device. The contact trace is electrically isolated from the rest of the PCB circuitry during a fabrication process by a separation distance between an exposed portion of the contact trace and an impedance trace. The contact finger and the exposed portion of the contact trace are plated with a common material to reduce galvanic etching of the contact trace during fabrication. The contact trace is then connected to the impedance trace using a solder joint.

Abstract: Disclosed is an electronic device having a display region and a peripheral region adjacent to the display region. The electronic device includes a first electrode disposed in the display region, a second electrode disposed in the display region, a circuit module disposed in the peripheral region, a first electrical trace, and a second electrical trace electrically insulated from the first electrical trace. The circuit module is electrically connected to the first electrode through the first electrical trace and provides a first driving voltage to the first electrical trace. The circuit module is electrically connected to the second electrode through the second electrical trace and provides a second driving voltage to the second electrical trace, and the first driving voltage is different from the second driving voltage. In a top view, the first electrical trace at least partially overlaps the second electrical trace.

Abstract: Systematic fault localization systems and methods are provided which utilize computational GDS-assisted navigation to accelerate physical fault analysis to identify systematic fault locations and patterns. In some embodiments, a method includes detecting a plurality of electrical fault regions of a plurality of dies of a semiconductor wafer. Decomposed Graphic Database System (GDS) cross-layer clips are generated which are associated with the plurality of electrical fault regions. A plurality of cross-layer common patterns is identified based on the decomposed GDS cross-layer clips. Normalized differentials may be determined for each of the cross-layer common patterns, and locations of hotspots in each of the dies may be identified based on the determined normalized differentials.

Abstract: A wireless charger, comprising: a thermal-conductive plastic cover; a first circuit board; and a metallic case, wherein the first circuit board are disposed in the metallic case, wherein a wind tunnel is formed between the thermal-conductive plastic cover and the circuit board for lowering the temperature of an electronic device that is wirelessly charged on the thermal-conductive plastic cover.

Abstract: Systematic fault localization systems and methods are provided which utilize computational GDS-assisted navigation to accelerate physical fault analysis to identify systematic fault locations and patterns. In some embodiments, a method includes detecting a plurality of electrical fault regions of a plurality of dies of a semiconductor wafer. Decomposed Graphic Database System (GDS) cross-layer clips are generated which are associated with the plurality of electrical fault regions. A plurality of cross-layer common patterns is identified based on the decomposed GDS cross-layer clips. Normalized differentials may be determined for each of the cross-layer common patterns, and locations of hotspots in each of the dies may be identified based on the determined normalized differentials.

Abstract: A wireless charger, comprising: a thermal-conductive plastic cover; a first circuit board; and a metallic case, wherein the first circuit board are disposed in the metallic case, wherein a wind tunnel is formed between the thermal-conductive plastic cover and the circuit board for lowering the temperature of an electronic device that is wirelessly charged on the thermal-conductive plastic cover.

Abstract: A wireless charger comprises a top cover; a metallic case; and a first thermoelectric cooler chip, disposed between a bottom surface of the top cover and a top surface of the metallic case to form a heat conductive path from the top cover to the metallic case via the first thermoelectric cooler chip for dissipating heat generated by an electronic device disposed on the top cover for wireless charging the electronic device.

Abstract: Systematic fault localization systems and methods are provided which utilize computational GDS-assisted navigation to accelerate physical fault analysis to identify systematic fault locations and patterns. In some embodiments, a method includes detecting a plurality of electrical fault regions of a plurality of dies of a semiconductor wafer. Decomposed Graphic Database System (GDS) cross-layer clips are generated which are associated with the plurality of electrical fault regions. A plurality of cross-layer common patterns is identified based on the decomposed GDS cross-layer clips. Normalized differentials may be determined for each of the cross-layer common patterns, and locations of hotspots in each of the dies may be identified based on the determined normalized differentials.

Abstract: A wafer coating system includes a wafer chuck, a flowing insulating material sprayer and a wafer tilting lifting pin. The wafer chuck has a carrier part and a rotating part, which the carrier part is mounted on the rotating part to carry a wafer, and the rotating part is configured to rotate with a predetermined axis. The flowing insulating material sprayer is above the wafer chuck and configured to spray a flowing insulating material to the wafer, and the wafer tilting lifting pin is configured to form a first acute angle between the wafer and direction of gravity.

Abstract: An electronic device includes a chassis, a first thermal cover, and a second thermal cover. The chassis is assembled with a motherboard and a recognition device. The motherboard includes a basic input/output system (BIOS) and an electronic component. The BIOS is electrically connected to the electronic component. A first operation parameter and a second operation parameter adapted to the electronic component are preset in the BIOS. When the first thermal cover covers the chassis, the BIOS drives the electronic component to be operated according to the first operation parameter. When the second thermal cover covers the chassis, the BIOS drives the electronic component to be operated according to the second operation parameter.

Abstract: An embodiment of the invention provides a method for forming a chip package which includes: providing a substrate having a first surface and a second surface, wherein at least two conducting pads are disposed on the first surface of the substrate; partially removing the substrate from the second surface of the substrate to form at least two holes extending towards the first surface, wherein the holes correspondingly and respectively align with one of the conducting pads; after the holes are formed, partially removing the substrate from the second substrate to form at least a recess extending towards the first surface, wherein the recess overlaps with the holes; forming an insulating layer on a sidewall and a bottom of the trench and on sidewalls of the holes; and forming a conducting layer on the insulating layer, wherein the conducting layer electrically contacts with one of the conducting pads.

Abstract: Among other things, an integrated circuit and method for routing electrical pathways of an integrated circuit is provided. The integrated circuit comprises a buffer chain coupling a first cell of the integrated circuit to a second cell of the integrated circuit. An electrical pathway coupling a first inverter of the buffer chain with a second inverter of the buffer chain extends through a first set of metal layers and is routed to form a pulse-like shape having an apex at a top layer of the first set.