Patents by Inventor Chien-Kang Chou
Chien-Kang Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20080111242Abstract: An integrated circuit chip includes a silicon substrate, a first circuit in or over said silicon substrate, a second circuit device in or over said silicon substrate, a dielectric structure over said silicon substrate, a first interconnecting structure in said dielectric structure, a first pad connected to said first node of said voltage regulator through said first interconnecting structure, a second interconnecting structure in said dielectric structure, a second pad connected to said first node of said internal circuit through said second interconnecting structure, a passivation layer over said dielectric structure, wherein multiple opening in said passivation layer exposes said first and second pads, and a third interconnecting structure over said passivation layer and over said first and second pads.Type: ApplicationFiled: September 29, 2007Publication date: May 15, 2008Applicant: MEGICA CorporationInventors: Mou-Shiung Lin, Jin-Yuan Lee, Chien-Kang Chou
-
Patent number: 7372161Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric and a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide post-passivation interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick passivation interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.Type: GrantFiled: December 20, 2004Date of Patent: May 13, 2008Assignee: Megica CorporationInventors: Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou
-
Patent number: 7355282Abstract: A system and method for forming post passivation metal structures is described. Metal interconnections and high quality electrical components, such as inductors, transformers, capacitors, or resistors are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.Type: GrantFiled: October 22, 2004Date of Patent: April 8, 2008Assignee: Megica CorporationInventors: Mou-Shiung Lin, Chien-Kang Chou, Chiu-Ming Chou
-
Publication number: 20080081458Abstract: An integrated circuit chip includes a silicon substrate, a first circuit in or over said silicon substrate, a second circuit device in or over said silicon substrate, a dielectric structure over said silicon substrate, a first interconnecting structure in said dielectric structure, a first pad connected to said first node of said voltage regulator through said first interconnecting structure, a second interconnecting structure in said dielectric structure, a second pad connected to said first node of said internal circuit through said second interconnecting structure, a passivation layer over said dielectric structure, wherein multiple opening in said passivation layer exposes said first and second pads, and a third interconnecting structure over said passivation layer and over said first and second pads.Type: ApplicationFiled: September 29, 2007Publication date: April 3, 2008Applicant: MEGICA CORPORATIONInventors: Mou-Shiung Lin, Jin-Yuan Lee, Chien-Kang Chou
-
Publication number: 20080080111Abstract: An integrated circuit chip includes a silicon substrate, a first circuit in or over said silicon substrate, a second circuit device in or over said silicon substrate, a dielectric structure over said silicon substrate, a first interconnecting structure in said dielectric structure, a first pad connected to said first node of said voltage regulator through said first interconnecting structure, a second interconnecting structure in said dielectric structure, a second pad connected to said first node of said internal circuit through said second interconnecting structure, a passivation layer over said dielectric structure, wherein multiple opening in said passivation layer exposes said first and second pads, and a third interconnecting structure over said passivation layer and over said first and second pads.Type: ApplicationFiled: September 29, 2007Publication date: April 3, 2008Applicant: MEGICA CORPORATIONInventors: Mou-Shiung Lin, Jin-Yuan Lee, Chien-Kang Chou
-
Publication number: 20080080113Abstract: An integrated circuit chip includes a silicon substrate, a first circuit in or over said silicon substrate, a second circuit device in or over said silicon substrate, a dielectric structure over said silicon substrate, a first interconnecting structure in said dielectric structure, a first pad connected to said first node of said voltage regulator through said first interconnecting structure, a second interconnecting structure in said dielectric structure, a second pad connected to said first node of said internal circuit through said second interconnecting structure, a passivation layer over said dielectric structure, wherein multiple opening in said passivation layer exposes said first and second pads, and a third interconnecting structure over said passivation layer and over said first and second pads.Type: ApplicationFiled: September 29, 2007Publication date: April 3, 2008Applicant: MEGICA CORPORATIONInventors: Mou-Shiung Lin, Jin-Yuan Lee, Chien-Kang Chou
-
Publication number: 20080080112Abstract: An integrated circuit chip includes a silicon substrate, a first circuit in or over said silicon substrate, a second circuit device in or over said silicon substrate, a dielectric structure over said silicon substrate, a first interconnecting structure in said dielectric structure, a first pad connected to said first node of said voltage regulator through said first interconnecting structure, a second interconnecting structure in said dielectric structure, a second pad connected to said first node of said internal circuit through said second interconnecting structure, a passivation layer over said dielectric structure, wherein multiple opening in said passivation layer exposes said first and second pads, and a third interconnecting structure over said passivation layer and over said first and second pads.Type: ApplicationFiled: September 29, 2007Publication date: April 3, 2008Applicant: MEGICA CORPORATIONInventors: Mou-Shiung Lin, Jin-Yuan Lee, Chien-Kang Chou
-
Publication number: 20080081457Abstract: An integrated circuit chip includes a silicon substrate, a first circuit in or over said silicon substrate, a second circuit device in or over said silicon substrate, a dielectric structure over said silicon substrate, a first interconnecting structure in said dielectric structure, a first pad connected to said first node of said voltage regulator through said first interconnecting structure, a second interconnecting structure in said dielectric structure, a second pad connected to said first node of said internal circuit through said second interconnecting structure, a passivation layer over said dielectric structure, wherein multiple opening in said passivation layer exposes said first and second pads, and a third interconnecting structure over said passivation layer and over said first and second pads.Type: ApplicationFiled: September 30, 2007Publication date: April 3, 2008Applicant: MEGICA CORPORATIONInventors: Mou-Shiung Lin, Jin-Yuan Lee, Chien-Kang Chou
-
Publication number: 20080079461Abstract: An integrated circuit chip includes a silicon substrate, a first circuit in or over said silicon substrate, a second circuit device in or over said silicon substrate, a dielectric structure over said silicon substrate, a first interconnecting structure in said dielectric structure, a first pad connected to said first node of said voltage regulator through said first interconnecting structure, a second interconnecting structure in said dielectric structure, a second pad connected to said first node of said internal circuit through said second interconnecting structure, a passivation layer over said dielectric structure, wherein multiple opening in said passivation layer exposes said first and second pads, and a third interconnecting structure over said passivation layer and over said first and second pads.Type: ApplicationFiled: September 29, 2007Publication date: April 3, 2008Applicant: MEGICA CORPORATIONInventors: Mou-Shiung Lin, Jin-Yuan Lee, Chien-Kang Chou
-
Publication number: 20080042297Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric and a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide post-passivation interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick passivation interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.Type: ApplicationFiled: October 23, 2007Publication date: February 21, 2008Applicant: MEGICA CORPORATIONInventors: Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou
-
Publication number: 20080045007Abstract: The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads.Type: ApplicationFiled: October 23, 2007Publication date: February 21, 2008Applicant: MEGICA CORPORATIONInventors: Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou
-
Publication number: 20070246834Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric and a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide post-passivation interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick passivation interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.Type: ApplicationFiled: June 13, 2007Publication date: October 25, 2007Inventors: Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou
-
Patent number: 7271489Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric and a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide post-passivation interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick passivation interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.Type: GrantFiled: October 12, 2004Date of Patent: September 18, 2007Assignee: Megica CorporationInventors: Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou
-
Publication number: 20070205520Abstract: A chip package includes a semiconductor substrate, a first metal pad over the semiconductor substrate, and a second metal pad over the semiconductor substrate. In a case, the first metal pad is tape automated bonded thereto, and the second metal pad is solder bonded thereto. In another case, the first metal pad is tape automated bonded thereto, and the second metal pad is wirebonded thereto. In another case, the first metal pad is solder bonded thereto, and the second metal pad is wirebonded thereto. In another case, the first metal pad is bonded to an external circuitry using an anisotropic conductive film, and the second metal pad is solder bonded thereto. In another case, the first metal pad is bonded to an external circuitry using an anisotropic conductive film, and the second metal pad is wirebonded thereto.Type: ApplicationFiled: March 2, 2007Publication date: September 6, 2007Applicant: MEGICA CORPORATIONInventors: Chien-Kang Chou, Chiu-Ming Chou, Li-Ren Lin, Hsin-Jung Lo
-
Publication number: 20070166993Abstract: A cylindrical bonding structure and its method of manufacture. The cylindrical bonding structure is formed over the bonding pad of a silicon chip and the chip is flipped over to connect with a substrate board in the process of forming a flip-chip package. The cylindrical bonding structure mainly includes a conductive pillar and a solder cap. The conductive pillar is formed over the bonding pad of the silicon chip and the solder cap is attached to the upper end of the conductive pillar. The solder cap has a melting point lower than the conductive pillar. The solder cap can be configured into a cylindrical, spherical or hemispherical shape. To fabricate the cylindrical bonding structure, a patterned mask layer having a plurality of openings that correspond in position to the bonding pads on the wafer is formed over a silicon wafer. Conductive material is deposited into the openings to form conductive pillars and finally a solder cap is attached to the end of each conductive pillar.Type: ApplicationFiled: March 13, 2007Publication date: July 19, 2007Applicant: MEGICA CORPORATIONInventors: Jin-Yuan Lee, Chien-Kang Chou, Shih-Hsiung Lin, Hsi-Shan Kuo
-
Publication number: 20070164430Abstract: The present invention proposes a circuit component structure, which comprises a semiconductor substrate, a fine-line metallization structure formed over the semiconductor substrate and having at least one metal pad, a passivation layer formed over the fine-line metallization structure with the metal pads exposed by the openings of the passivation layer, at least one carbon nanotube layer formed over the fine-line metallization structure and the passivation layer and connecting with the metal pads. The present invention is to provide a carbon nanotube circuit component structure and a method for fabricating the same, wherein the circuit of a semiconductor element is made of an electrically conductive carbon nanotube, and the circuit of the semiconductor element can thus be made finer and denser via the superior electric conductivity, flexibility and strength of the carbon nanotube.Type: ApplicationFiled: November 27, 2006Publication date: July 19, 2007Applicant: MEGICA CorporationInventors: Mou-Shiung Lin, Chien-Kang Chou, Hsin-Jung Lo
-
Publication number: 20070096313Abstract: The invention provides a semiconductor chip comprising an interconnecting structure over said passivation layer. The interconnecting structure comprises a first contact pad connected to a second contact pad exposed by an opening in a passivation layer.Type: ApplicationFiled: October 28, 2005Publication date: May 3, 2007Inventors: Chiu-Ming Chou, Chien-Kang Chou, Ching-San Lin, Mou-Shiung Lin, Hsin-Jung Lo
-
Patent number: 7208834Abstract: A cylindrical bonding structure and its method of manufacture. The cylindrical bonding structure is formed over the bonding pad of a silicon chip and the chip is flipped over to connect with a substrate board in the process of forming a flip-chip package. The cylindrical bonding structure mainly includes a conductive pillar and a solder cap. The conductive pillar is formed over the bonding pad of the silicon chip and the solder cap is attached to the upper end of the conductive pillar. The solder cap has a melting point lower than the conductive pillar. The solder cap can be configured into a cylindrical, spherical or hemispherical shape. To fabricate the cylindrical bonding structure, a patterned mask layer having a plurality of openings that correspond in position to the bonding pads on the wafer is formed over a silicon wafer. Conductive material is deposited into the openings to form conductive pillars and finally a solder cap is attached to the end of each conductive pillar.Type: GrantFiled: June 22, 2004Date of Patent: April 24, 2007Assignee: Megica CorporationInventors: Jin-Yuan Lee, Chien-Kang Chou, Shih-Hsiung Lin, Hsi-Shan Kuo
-
Publication number: 20070069347Abstract: A semiconductor chip comprises a first MOS device, a second MOS device, a first metallization structure connected to said first MOS device, a second metallization structure connected to said second MOS device, a passivation layer over said first and second MOS devices and over said first and second metallization structures, and a third metallization structure connecting said first and second metallization structures.Type: ApplicationFiled: September 24, 2006Publication date: March 29, 2007Inventors: Mou-Shiung Lin, Chien-Kang Chou, Hsin-Jung Lo
-
Publication number: 20070045855Abstract: A method for fabricating a circuitry component comprises depositing a first metal layer over a substrate; forming a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposing said first metal layer; depositing a second metal layer over said first metal layer exposed by said first opening; removing said first pattern-defining layer; forming a second pattern-defining layer over said second metal layer, a second opening in said second pattern-defining layer exposing said second metal layer; depositing a third metal layer over said second metal layer exposed by said second opening; removing said second pattern-defining layer; removing said first metal layer not under said second metal layer; and forming a polymer layer over said second metal layer, wherein said third metal layer is used as a metal bump bonded to an external circuitry.Type: ApplicationFiled: July 24, 2006Publication date: March 1, 2007Inventors: Hsin-Jung Lo, Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou