Patents by Inventor Chien-Tung Yu

Chien-Tung Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230386951
    Abstract: In an embodiment, a package including: a redistribution structure including a first dielectric layer and a first conductive element disposed in the first dielectric layer; a first semiconductor device bonded to the redistribution structure, wherein the first semiconductor device includes a first corner; and an underfill disposed over the redistribution structure and including a first protrusion extending into the first dielectric layer of the redistribution structure, wherein the first protrusion of the underfill overlaps the first corner of the first semiconductor device in a plan view.
    Type: Application
    Filed: May 31, 2022
    Publication date: November 30, 2023
    Inventors: Yu-Sheng Lin, Chien-Tung Yu, Chia-Hsiang Lin, Chin-Hua Wang, Shin-Puu Jeng
  • Publication number: 20230307338
    Abstract: A method includes forming a redistribution structure, wherein forming the redistribution structure includes forming a first conductive material on a portion of a first seed layer, forming a mask over the first seed layer and the first conductive material, wherein an opening in the mask at least partially exposes the first conductive material, forming a first conductive via in the opening, etching portions of the first seed layer using the first conductive material as an etching mask, depositing a first insulating layer over the first conductive via, the first conductive material and remaining portions of the first seed layer, and etching the first insulating layer such that a portion of the first conductive via protrudes above a top surface of the first insulating layer, and attaching a first die to the redistribution structure using first electrical connectors.
    Type: Application
    Filed: March 28, 2022
    Publication date: September 28, 2023
    Inventors: Chien-Tung Yu, Chia-Hsiang Lin, Chi-Pu Lin, Shin-Puu Jeng
  • Patent number: 11606875
    Abstract: Embodiments described herein relate to a system for securing a computing device component. The system may include the computing device component that includes: a base component comprising a pass through hole, a rotating member coupled to the base component and adapted to rotate about an axis, a lever body that includes: a base-holding portion adapted to be positioned around the base component, and a lever extension at a first end of the lever body and extending substantially orthogonally in a direction substantially orthogonal to the axis, a lever locking component coupled to the lever body and that includes: a locking actuator, and an inserting component adapted to insert into the pass-through hole when the locking actuator is in a locked position, wherein when a force is applied to the lever extension, the base component rotates about the axis.
    Type: Grant
    Filed: October 22, 2021
    Date of Patent: March 14, 2023
    Assignee: Dell Products L.P.
    Inventor: Chien Tung-Yu
  • Patent number: 9915983
    Abstract: A component carrier coupling system includes a carrier base including a carrier wall. A handle is coupled to the carrier wall by a plurality of link elements that each include a first end rotatably connected to the handle and a second end rotatably connected to the carrier wall. The handle is maintained in a substantially parallel orientation to the carrier wall when the plurality of link elements are rotated in a first direction that moves the handle away from the carrier wall, and in a second direction that is opposite the first direction and that moves the handle immediately adjacent the carrier wall. A cam element is provided on at least one of the plurality of link elements and engages a component enclosure when the carrier base is located in the component enclosure and the plurality of link elements are rotated in the second direction.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: March 13, 2018
    Assignee: Dell Products L.P.
    Inventors: Chien Tung Yu, Yen Ming Wu, Ju Hao Lee
  • Publication number: 20170185111
    Abstract: A component carrier coupling system includes a carrier base including a carrier wall. A handle is coupled to the carrier wall by a plurality of link elements that each include a first end rotatably connected to the handle and a second end rotatably connected to the carrier wall. The handle is maintained in a substantially parallel orientation to the carrier wall when the plurality of link elements are rotated in a first direction that moves the handle away from the carrier wall, and in a second direction that is opposite the first direction and that moves the handle immediately adjacent the carrier wall. A cam element is provided on at least one of the plurality of link elements and engages a component enclosure when the carrier base is located in the component enclosure and the plurality of link elements are rotated in the second direction.
    Type: Application
    Filed: December 28, 2015
    Publication date: June 29, 2017
    Inventors: Chien Tung Yu, Yen Ming Wu, Ju Hao Lee
  • Patent number: 7459386
    Abstract: A method for forming solder bumps (or solder balls after reflow) of improved height and reliability is provided. In one embodiment, a semiconductor substrate having at least one contact pad and an upper passivation layer having at least one opening formed therein exposing a portion of the contact pad is provided. A layer of under bump metal (UBM) is formed above the passivation layer and the contact pad. A first patterned and etched photoresist layer is provided above the UBM layer, the first patterned and etched photoresist layer defining at least one first opening therein. A second patterned and etched photoresist layer is provided above the first patterned and etched photoresist layer, the second patterned and etched photoresist layer defining at least one second opening therein, the second opening being wider than the first opening. A solder material is filled in the at least one first opening and substantially filled in the at least one second opening.
    Type: Grant
    Filed: November 16, 2004
    Date of Patent: December 2, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Hsin Tseng, Gil Huang, Huei-Mei Yu, Chia-Jen Cheng, Ken Sun, Chien-Tung Yu, Blenny Chang, Chih Yang Chan, Jian-Wen Luo, Owen Chen
  • Patent number: 7378724
    Abstract: A method for providing a cavity structure on a semiconductor device is provided. The method of forming the cavity structure, which may be particularly useful in packaging an image sensor, includes forming a spacer layer over a substrate. The spacer layer may be formed from a photo-sensitive material which may be patterned using photolithography techniques to form cavity walls surrounding dies on the wafer. A packaging layer, such as a substantially transparent layer, may be placed directly upon the cavity walls prior to curing. In another embodiment, the cavity walls are cured, an adhesive is applied to a surface of the cavity walls, and the packaging layer placed upon the adhesive. Thereafter, the wafer may be diced and the individual dies may be packaged for use.
    Type: Grant
    Filed: June 24, 2005
    Date of Patent: May 27, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiu-Mei Yu, Gil Huang, Chien-Tung Yu, Owen Chen
  • Publication number: 20060213804
    Abstract: A method for providing a cavity structure on a semiconductor device is provided. The method of forming the cavity structure, which may be particularly useful in packaging an image sensor, includes forming a spacer layer over a substrate. The spacer layer may be formed from a photo-sensitive material which may be patterned using photolithography techniques to form cavity walls surrounding dies on the wafer. A packaging layer, such as a substantially transparent layer, may be placed directly upon the cavity walls prior to curing. In another embodiment, the cavity walls are cured, an adhesive is applied to a surface of the cavity walls, and the packaging layer placed upon the adhesive. Thereafter, the wafer may be diced and the individual dies may be packaged for use.
    Type: Application
    Filed: June 24, 2005
    Publication date: September 28, 2006
    Inventors: Hsiu-Mei Yu, Gil Huang, Chien-Tung Yu, Owen Chen
  • Publication number: 20060105560
    Abstract: A method for forming solder bumps (or solder balls after reflow) of improved height and reliability is provided. In one embodiment, a semiconductor substrate having at least one contact pad and an upper passivation layer having at least one opening formed therein exposing a portion of the contact pad is provided. A layer of under bump metal (UBM) is formed above the passivation layer and the contact pad. A first patterned and etched photoresist layer is provided above the UBM layer, the first patterned and etched photoresist layer defining at least one first opening therein. A second patterned and etched photoresist layer is provided above the first patterned and etched photoresist layer, the second patterned and etched photoresist layer defining at least one second opening therein, the second opening being wider than the first opening. A solder material is filled in the at least one first opening and substantially filled in the at least one second opening.
    Type: Application
    Filed: November 16, 2004
    Publication date: May 18, 2006
    Inventors: Li-Hsin Tseng, Gil Huang, Huei-Mei Yu, Chia-Jen Cheng, Ken Sun, Chien-Tung Yu, Blenny Chang, Chih Chan, Jian-Wen Luo, Owen Chen