Abstract: A structure of controlled pipeline logic is disclosed. A random noise generator is added to the controlled pipeline logic. Moreover, each combinational logic element of the controlled pipeline logic is appended with an active bit. When no input flows into the controlled pipeline logic, the random noise generator will generate random noises, and the active bit will enforce the combinational logic element to accept the random noise as an input so that the controlled pipeline logic is always sustained in the active condition. The controlled pipeline logic is not exposing the internal functions thereof and avoiding improper monitoring and observation.

Abstract: The present invention relates to a DRAM memory page operation method and its structure. The disclosed method comprises a set up procedure and an operation procedure. The set up procedure tests and finds out whether any deficit exists in the memory page of the memory and establishes a table of look-aside buffer that indicates defective locations and the corresponding new locations. The real operation procedure is executed after the set up procedure completes. It establishes a fast page lookup table according to results in the set up procedure for instructing the memory page or memory unit to operate in the normal access mode or the page operation mode. Good memory pages then replace bad memory pages according to the records in the fast page lookup table and the bad memory pages are moved to addresses at the very end of the memory so that the memory can operate even with deficits. Thus, no deficit in a single DRAM memory page/unit will halt the whole system.

Abstract: A method of IC packing/unpacking for preserving and updating data stored in the IC and the structure thereof is disclosed. The method is able to encase the IC to prevent intentional piracy and allow data preservation and update. The structure has an upper plate (10) having a trough (12) defined therein; a lower plate (20) detachably connected with the upper plate (10); a PCB (30) sandwiched between the upper plate (10) and the lower plate (20) and forming an electrical connection with the upper plate (10); an interface (60) detachably inserted into the trough (12) and being able to receive data therein; and a controller (50) electrically connected with the interface (60) for coding the interface (60).

Abstract: A data-processing system with an enhanced system controller supporting memory-remapping function. The system controller has an access control circuit, a page/remapping management circuit and an open/remapped address table. The open/remapped address table is used to store mapping tables for indicating the mapping relation of memory segments and addresses dedicated to peripheral devices. The page/remapping management circuit should maintain and use the mapping tables in various operating mode. In addition, the page/remapping management circuit can redirect access requests to proper memory segments according to the mapping table corresponding to the current operating mode. Therefore, peripheral devices can effectively access and process the data stored in various memory segments by the change of the operating modes, not by physical data transfer.

Abstract: An integrated circuit (IC) chip security box includes a top cover member and a bottom cover member respectively mounted to top and bottom sides of a circuit board to enclose an IC chip mounted to the circuit board. The cover members are made of conductive material for blocking radio frequency emission from the IC chip. Bolts secure the cover members to the circuit board. Conductive members are formed on one of the cover members and the circuit board and engage with each other when the security box is mounted to the circuit board thereby forming an electrical loop. Unauthorized opening of the security box breaks the electrical loop thereby causing a signal to the IC chip to initiate a purging process which deletes program codes written in the chip and prevents unauthorized copy of the codes.

Abstract: A system and method for reducing data traffic between the processor and the system controller in a data processing system during the execution of a vector or matrix instruction. When the processor receives an operation command requiring that a large quantity of data be processed, the processor issues a local operation request containing the desired operation, addressing information of the operands and a destination location for the result to the system. The system controller includes a local operation unit for locally executing the local operation request issued from the processor. Because the operand data associated with the operation need not be transferred over the system bus connected between the processor and the system controller, the data traffic between the processor and the system controller is reduced.

Abstract: A buffer management device and method for improving buffer usage and access performance in a data processing system. A buffer device is located between two components in the data processing system and can be operated in the line mode and page mode. The buffer device typically comprises a number of memory blocks for temporarily storing the transmitted data, first tag memories, second tag memories and a mode-switching circuit. Each of the memory blocks includes a plurality of memory segments. In the line mode, the first tag memories store the addressing information and the memory blocks serve as the data storage unit. In the page mode, the second tag memories store the addressing information and the memory segments serve as the data storage unit. Therefore, data carried by different requests can be merged into the same memory block.

Abstract: A security mechanism for an IC packing box includes a plurality of detecting circuit boards in the packing box. These circuit boards are arranged by pairs. The upper circuit board has etched vertical wiring, and the lower circuit board has etched horizontal wiring. The vertical wiring and the horizontal wiring are connected through zero-ohm resistors for forming a crossing security net. The security net has a plug to connect with a socket slot of an IC circuit board. At least one detecting lead of the IC can send random signals to the detecting circuit boards for completing an electric loop. Foreign invasion upon the packing box is determined by evaluating the flow of the electric loop.

Abstract: A computer system having a genetic code that cannot be directly accessed by processors or other master devices. In the computer system of the invention, a genetic code display procedure (GDP) and a genetic code setup procedure (GSP) are required to maintain the genetic code. In the GDP, the genetic code is transmitted to a monitor under the control of the processor, but cannot be directly accessed by the processor. In the GSP, a new key-in genetic code is transmitted to a memory device storing the genetic code, but cannot be directly accessed by the processor. Therefore, the genetic code of the computer system is secure and maintainable.