Abstract: A gaming key mode adjusting method and an electronic device are provided. The gaming key mode adjusting method includes: retrieving a display image; determining that the display image corresponds to a gaming scenario; obtain a key mode corresponding to the gaming scenario and process a keyboard input signal according to the key mode. In the key mode, key travels correspond to a plurality of key press values.

Abstract: A gaming key mode adjusting method and an electronic device are provided. The gaming key mode adjusting method includes: retrieving a display image; determining that the display image corresponds to a gaming scenario; obtain a key mode corresponding to the gaming scenario and process a keyboard input signal according to the key mode. In the key mode, key travels correspond to a plurality of key press values.

Abstract: The present invention provides a high voltage device and a manufacturing method thereof. The high voltage device includes: a semiconductor layer, a drift oxide region, a well, a body region, a gate, at least one sub-gate, a source, and a drain. The drift oxide region is located on a drift region in an operation region. The sub-gate is formed on the drift oxide region right above the drift region. The sub-gate is parallel with the gate. A conductive layer of the gate has a first conductivity type, and a conductive layer of the sub-gate has a second conductivity type or is an intrinsic semiconductor structure.

Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type, wherein the semiconductor substrate includes a first region and a second region. The semiconductor device also includes a buried layer disposed in the first region of the semiconductor substrate and having the first conductivity type, wherein the buried layer has a dopant concentration that is greater than that of the semiconductor substrate. The semiconductor device further includes an epitaxial layer disposed on the semiconductor substrate, and a first element disposed on the first region of the semiconductor substrate, wherein the first element includes a bipolar-complementary metal oxide semiconductor (CMOS)-double diffused metal oxide semiconductor (DMOS) (BCD) transistor. In addition, the semiconductor device includes a second element disposed on the second region of the semiconductor substrate, wherein the second element includes an ultra-high voltage (UHV) transistor.

Abstract: A semiconductor device including a substrate, a first doped region, a second doped region, a gate, and a gate dielectric layer is provided. The substrate has a first conductive type. The first doped region is formed in the substrate and has a second conductive type. The second doped region is formed in the substrate and has the second conductive type. The gate is formed on the substrate and is disposed between the first and second doped regions. The gate dielectric layer is formed on the substrate and is disposed between the gate and the substrate. The gate dielectric layer includes a first region and a second region. The depth of the first region is different from the depth of the second region.

Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type, wherein the semiconductor substrate includes a first region and a second region. The semiconductor device also includes a buried layer disposed in the first region of the semiconductor substrate and having the first conductivity type, wherein the buried layer has a dopant concentration that is greater than that of the semiconductor substrate. The semiconductor device further includes an epitaxial layer disposed on the semiconductor substrate, and a first element disposed on the first region of the semiconductor substrate, wherein the first element includes a bipolar-complementary metal oxide semiconductor (CMOS)-double diffused metal oxide semiconductor (DMOS) (BCD) transistor. In addition, the semiconductor device includes a second element disposed on the second region of the semiconductor substrate, wherein the second element includes an ultra-high voltage (UHV) transistor.

Abstract: A semiconductor device including a substrate, a first doped region, a second doped region, a gate, and a gate dielectric layer is provided. The substrate has a first conductive type. The first doped region is formed in the substrate and has a second conductive type. The second doped region is formed in the substrate and has the second conductive type. The gate is formed on the substrate and is disposed between the first and second doped regions. The gate dielectric layer is formed on the substrate and is disposed between the gate and the substrate. The gate dielectric layer includes a first region and a second region. The depth of the first region is different from the depth of the second region.

Abstract: Embodiments of the disclosure relate to an enhanced-mode high electron mobility transistor. The enhanced-mode high electron mobility transistor includes a substrate, a first III-V semiconductor layer disposed on the substrate, a second III-V semiconductor layer disposed on the first III-V semiconductor layer, a third III-V semiconductor layer disposed on the second III-V semiconductor layer, an amorphous region extending from the third III-V semiconductor layer into the second III-V semiconductor layer and the first III-V semiconductor layer to serve as an isolation region, and a gate electrode disposed in the amorphous region. The second III-V semiconductor layer and the third III-V semiconductor layer include different materials to form a heterojunction.

Abstract: A method for manufacturing a semiconductor device includes forming a first gate structure on a semiconductor substrate. The first gate structure includes a first gate dielectric layer and a first gate electrode layer formed thereon. The method also includes forming an insulating material layer on the semiconductor substrate, wherein the semiconductor substrate and the first gate structure are covered by the insulating material layer. The method further includes removing a portion of the insulating material layer in a high-voltage element region to form a second gate dielectric layer in the high-voltage element region on the semiconductor substrate, and forming a second gate electrode layer on the second gate dielectric layer.

Abstract: A semiconductor device includes a first gallium nitride layer disposed on a semiconductor substrate, wherein the first gallium nitride layer has a first conductivity type. The semiconductor device also includes a second gallium nitride layer disposed on the first gallium nitride layer, wherein the second gallium nitride layer has the first conductivity type, and the first gallium nitride layer has a dopant concentration which is greater than that of the second gallium nitride layer. The semiconductor device further includes an anode electrode disposed on the second gallium nitride layer, a cathode electrode disposed on and in direct contact with the first gallium nitride layer, and an insulating region disposed on and in direct contact with the first gallium nitride layer, wherein the insulating region is located between the cathode electrode and the second gallium nitride layer.

Abstract: High-voltage semiconductor devices are provided. The high-voltage semiconductor device includes a substrate and an isolation structure in the substrate. The high-voltage semiconductor device includes a gate structure disposed on the substrate, wherein the gate structure is separated from the isolation structure by a distance. The high-voltage semiconductor device also includes a metal electrode disposed on the gate structure, wherein the metal electrode extends to directly above the isolation structure. The high-voltage semiconductor device further includes an interconnection structure including the lowest metal layer, wherein the metal electrode is between the lowest metal layer and the gate structure. Methods of manufacturing the high-voltage semiconductor device are also provided.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate; an epitaxial layer; a first conductive type first well region disposed in the substrate and the epitaxial layer; a second conductive type first buried layer and a second conductive type second buried layer disposed at opposite sides of the first conductive type first well region, respectively; a first conductive type second well region disposed in the epitaxial layer and being in direct contact with the first conductive type first well region; a second conductive type third buried layer disposed in the first conductive type first well region and/or the first conductive type second well region; a second conductive type doped region disposed in the first conductive type second well region; a gate structure; a drain contact plug; and a source contact plug.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate; an epitaxial layer; a first conductive type first well region disposed in the substrate and the epitaxial layer; a second conductive type first buried layer and a second conductive type second buried layer disposed at opposite sides of the first conductive type first well region, respectively; a first conductive type second well region disposed in the epitaxial layer and being in direct contact with the first conductive type first well region; a second conductive type third buried layer disposed in the first conductive type first well region and/or the first conductive type second well region; a second conductive type doped region disposed in the first conductive type second well region; a gate structure; a drain contact plug; and a source contact plug.

Abstract: The present invention discloses a vertical semiconductor device and a manufacturing method thereof. The vertical semiconductor device includes: a substrate having a first surface and a second surface, the substrate including a conductive array formed by multiple conductive plugs through the substrate; a semiconductor layer formed on the first surface, the semiconductor layer having a third surface and a fourth surface, wherein the fourth surface faces the first surface; a first electrode formed on the third surface; and a second electrode formed on the second surface for electrically connecting to the conductive array.

Abstract: The present invention discloses a semiconductor composite film with a heterojunction and a manufacturing method thereof. The semiconductor composite film includes: a semiconductor substrate; and a semiconductor epitaxial layer, which is formed on the semiconductor substrate, and it has a first surface and a second surface opposite to each other, wherein the heterojunction is formed between the first surface and the semiconductor substrate, and wherein the semiconductor epitaxial layer further includes at least one recess, which is formed by etching the semiconductor epitaxial layer from the second surface toward the first surface. The recess is for mitigating a strain in the semiconductor composite film.

Abstract: The present invention discloses a vertical semiconductor device and a manufacturing method thereof. The vertical semiconductor device includes: a substrate having a first surface and a second surface, the substrate including a conductive array formed by multiple conductive plugs through the substrate; a semiconductor layer formed on the first surface, the semiconductor layer having a third surface and a fourth surface, wherein the fourth surface faces the first surface; a first electrode formed on the third surface; and a second electrode formed on the second surface for electrically connecting to the conductive array.

Abstract: The present invention discloses a vertical semiconductor device and a manufacturing method thereof. The vertical semiconductor device includes: a substrate having a first surface and a second surface, the substrate including a conductive array formed by multiple conductive plugs through the substrate; a semiconductor layer formed on the first surface, the semiconductor layer having a third surface and a fourth surface, wherein the fourth surface faces the first surface; a first electrode formed on the third surface; and a second electrode formed on the second surface for electrically connecting to the conductive array.

Abstract: The present invention discloses an insulated gate bipolar transistor (IGBT) and a manufacturing method thereof. The IGBT includes: a gallium nitride (GaN) substrate, a first GaN layer with a first conductive type, a second GaN layer with a first conductive type, a third GaN layer with a second conductive type or an intrinsic conductive type, and a gate formed on the GaN substrate. The first GaN layer is formed on the GaN substrate and has a side wall vertical to the GaN substrate. The second GaN layer is formed on the GaN substrate and is separated from the first GaN layer by the gate. The third GaN layer is formed on the first GaN layer and is separated from the GaN substrate by the first GaN layer. The gate has a side plate adjacent to the side wall in a lateral direction to control a channel.

Abstract: The present invention discloses an insulated gate bipolar transistor (IGBT) and a manufacturing method thereof. The IGBT includes: a gallium nitride (GaN) substrate, a first GaN layer with a first conductive type, a second GaN layer with a first conductive type, a third GaN layer with a second conductive type or an intrinsic conductive type, and a gate formed on the GaN substrate. The first GaN layer is formed on the GaN substrate and has a side wall vertical to the GaN substrate. The second GaN layer is formed on the GaN substrate and is separated from the first GaN layer by the gate. The third GaN layer is formed on the first GaN layer and is separated from the GaN substrate by the first GaN layer. The gate has a side plate adjacent to the side wall in a lateral direction to control a channel.

Abstract: The present invention discloses a semiconductor composite film with a heterojunction and a manufacturing method thereof. The semiconductor composite film includes: a semiconductor substrate; and a semiconductor epitaxial layer, which is formed on the semiconductor substrate, and it has a first surface and a second surface opposite to each other, wherein the heterojunction is formed between the first surface and the semiconductor substrate, and wherein the semiconductor epitaxial layer further includes at least one recess, which is formed by etching the semiconductor epitaxial layer from the second surface toward the first surface. The recess is for mitigating a strain in the semiconductor composite film.