Patents by Inventor Chien-Hsin Lee
Chien-Hsin Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240152671Abstract: A violation checking method includes generating a violation log report for a design, classifying violation logs in the violation log report into high-risk logs and low-risk logs by a machine learning model, reviewing the high-risk logs, and modifying the design if at least one bug is identified in the high-risk logs.Type: ApplicationFiled: November 3, 2023Publication date: May 9, 2024Applicant: MEDIATEK INC.Inventors: Chi-Ming Lee, Chung-An Wang, Cheok Yan Goh, Chia-Cheng Tsai, Chien-Hsin Yeh, Chia-Shun Yeh, Chin-Tang Lai
-
Publication number: 20240155758Abstract: An electronic device is provided. The electronic device includes a first dielectric layer, an electronic element, an encapsulant, and a second dielectric layer. The first dielectric layer has a first coefficient of thermal expansion (CTE). The electronic element is disposed over the first dielectric layer. The encapsulant encapsulates the electronic element and has a second CTE. The second dielectric layer is disposed over the encapsulant and having a third CTE. The second CTE ranges between the first CTE and the third CTE.Type: ApplicationFiled: November 4, 2022Publication date: May 9, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chien Lin CHANG CHIEN, Yuan-Chun TAI, Yu Hsin CHANG CHIEN, Chiu-Wen LEE, Chang Chi LEE
-
Publication number: 20240088042Abstract: A semiconductor structure includes a dielectric layer over a substrate, a via conductor over the substrate and in the dielectric layer, and a first graphene layer disposed over the via conductor. In some embodiments, a top surface of the via conductor and a top surface of the dielectric layer are level. In some embodiments, the first graphene layer overlaps the via conductor from a top view. In some embodiments, the semiconductor structure further includes a second graphene layer under the via conductor and a third graphene layer between the dielectric layer and the via conductor. In some embodiments, the second graphene layer is between the substrate and the via conductor.Type: ApplicationFiled: January 11, 2023Publication date: March 14, 2024Inventors: SHU-WEI LI, HAN-TANG HUNG, YU-CHEN CHAN, CHIEN-HSIN HO, SHIN-YI YANG, MING-HAN LEE, SHAU-LIN SHUE
-
Patent number: 11508117Abstract: An extended reality space generating apparatus and method are provided. The extended reality space generating apparatus generates a plurality of plane plates, a plate coordinate and a normal vector corresponding to each of the plane plates based on a plurality of point clouds, wherein the point clouds correspond to a real space. The extended reality space generating apparatus compares the plate coordinates and the normal vectors of the plane plates in a visual window to generate an effective plane plate set. The extended reality space generating apparatus generates an extended reality space corresponding to the real space based on the effective plane plate set.Type: GrantFiled: November 22, 2021Date of Patent: November 22, 2022Assignee: INSTITUTE FOR INFORMATION INDUSTRYInventors: Shang-Ming Wang, Chi-Hsien Liu, Chien-Hsin Lee
-
Patent number: 11315746Abstract: A method for adjusting an optical switch keyboard and an optical switch keyboard using the adjusting method are provided. The optical switch keyboard has a number of key units. The method includes the following steps. A scan signal is applied to one of a number of scan lines by a control unit at a first scan time point. A light is emitted by a light source according to the scan signal. A light emitted by the light source is detected by a detecting element to generate a detecting electric signal. The detecting electric signal is read by the control unit to obtain a first read signal voltage. When the first read signal voltage is outside the voltage range of the pressed state of the key unit, the period of the scan signal is increased by a first predetermined amount by the control unit to obtain an adjusted scan signal.Type: GrantFiled: November 13, 2020Date of Patent: April 26, 2022Assignee: Darfon Electronics Corp.Inventor: Chien-Hsin Lee
-
Publication number: 20210202193Abstract: A method for adjusting an optical switch keyboard and an optical switch keyboard using the adjusting method are provided. The optical switch keyboard has a number of key units. The method includes the following steps. A scan signal is applied to one of a number of scan lines by a control unit at a first scan time point. A light is emitted by a light source according to the scan signal. A light emitted by the light source is detected by a detecting element to generate a detecting electric signal. The detecting electric signal is read by the control unit to obtain a first read signal voltage. When the first read signal voltage is outside the voltage range of the pressed state of the key unit, the period of the scan signal is increased by a first predetermined amount by the control unit to obtain an adjusted scan signal.Type: ApplicationFiled: November 13, 2020Publication date: July 1, 2021Applicant: Darfon Electronics Corp.Inventor: Chien-Hsin LEE
-
Patent number: 10964687Abstract: A fin field effect transistor (FinFET) ESD device is disclosed. The device may include: a substrate; a silicon-controlled rectifier (SCR) over the substrate, the SCR including: a p-well region over the substrate; an n-well region laterally abutting the p-well region over the substrate; a first P+ doped region over the p-well region; a first N+ doped region over the p-well region; and a second N+ doped region over the p-well region; and a Schottky diode electrically coupled to the n-well region, wherein the Schottky diode spans the n-well region and the p-well region, and wherein the Schottky diode controls electrostatic discharge (ESD) between the second N+ doped region and the n-well region.Type: GrantFiled: February 8, 2017Date of Patent: March 30, 2021Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Chien-Hsin Lee, Mahadeva Iyer Natarajan, Manjunatha Prahbu
-
Patent number: 10833012Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to transistor structures and methods of manufacture. The structure includes active metal lines separated by electrically floating metal layers which have a width less than a width of the active metal lines.Type: GrantFiled: September 30, 2019Date of Patent: November 10, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Chien-Hsin Lee, Haojun Zhang, Mahadeva Iyer Natarajan
-
Patent number: 10790276Abstract: Methods, apparatus, and systems relating to a MOSFET with ESD resistance, specifically, to a semiconductor device comprising a field-effect transistor (FET) comprising a gate, a source, and a drain, all extending parallel to each other in a first direction; at least one source electrostatic discharge (ESD) protection circuit; a source terminal disposed above and in electrical contact with the at least one source ESD protection circuit, wherein the source terminal extends in the first direction; at least one drain ESD protection circuit; and a drain terminal disposed above and in electrical contact with the at least one drain ESD protection circuit, wherein the drain terminal extends in the first direction.Type: GrantFiled: September 28, 2018Date of Patent: September 29, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Chien-Hsin Lee, Manjunatha Prabhu, Mahadeva Iyer Natarajan
-
Patent number: 10763250Abstract: The SCR-based ESD device has a 4-layered PNPN structure (NPN and PNP junction transistors) disposed in SOI having first and second device wells (N-well and P-well) abut forming a NP junction near a midline. First and second contact regions disposed in device wells are coupled to high and low power sources (I/O pad and ground). Internal isolation regions (shallower STI) extending partially not touching the bottom of surface substrate separate the first and second contact regions. A vertical gate is disposed over the NP junction or over a shallower STI which overlaps the junction and separate the second contact regions in x-direction. One or more horizontal gates separate the second contact regions in y-direction and guide the device wells underneath the shallower STI to outer edges to connect with the first contact regions for body contacts. A process for forming the device is also disclosed and is compatible with CMOS processes.Type: GrantFiled: November 15, 2019Date of Patent: September 1, 2020Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Wei Gao, Shaoqiang Zhang, Chien-Hsin Lee
-
Patent number: 10741542Abstract: High-voltage semiconductor devices with electrostatic discharge (ESD) protection and methods of fabrication are provided. The semiconductor devices include a plurality of transistors on a substrate patterned with one or more common gates extending across a portion of the substrate, and a plurality of first S/D contacts and a plurality of second S/D contacts associated with the common gate(s). The second S/D contacts are disposed over a plurality of carrier-doped regions within the substrate. One or more floating nodes are disposed above the substrate and, at least in part, between second S/D contacts to facilitate defining the plurality of carrier-doped regions within the substrate. For instance, the carrier-doped regions may be defined from a mask with a common carrier-region opening, with the floating node(s) intersecting the common carrier-region opening and facilitating defining, along with the common opening, the plurality of separate carrier-doped regions.Type: GrantFiled: August 6, 2018Date of Patent: August 11, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Chien-Hsin Lee, Xiangxiang Lu, Manjunatha Prabhu, Mahadeva Iyer Natarajan
-
Patent number: 10651166Abstract: E-fuse cells and methods for protecting e-fuses are provided. An exemplary e-fuse cell includes an e-fuse having a first end coupled to a source node and a second end selectively coupled to a ground. Further, the exemplary e-fuse includes a selectively activated shunt path from the source node to the ground. Also, the exemplary e-fuse includes a device for activating the shunt path in response to an electrical overstress event.Type: GrantFiled: May 31, 2017Date of Patent: May 12, 2020Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Handoko Linewih, Chien-Hsin Lee
-
Publication number: 20200083213Abstract: The SCR-based ESD device has a 4-layered PNPN structure (NPN and PNP junction transistors) disposed in SOI having first and second device wells (N-well and P-well) abut forming a NP junction near a midline. First and second contact regions disposed in device wells are coupled to high and low power sources (I/O pad and ground). Internal isolation regions (shallower STI) extending partially not touching the bottom of surface substrate separate the first and second contact regions. A vertical gate is disposed over the NP junction or over a shallower STI which overlaps the junction and separate the second contact regions in x-direction. One or more horizontal gates separate the second contact regions in y-direction and guide the device wells underneath the shallower STI to outer edges to connect with the first contact regions for body contacts. A process for forming the device is also disclosed and is compatible with CMOS processes.Type: ApplicationFiled: November 15, 2019Publication date: March 12, 2020Inventors: Wei GAO, Shaoqiang ZHANG, Chien-Hsin LEE
-
Patent number: 10573639Abstract: The SCR-based ESD device has a 4-layered PNPN structure (NPN and PNP junction transistors) disposed in SOI having first and second device wells (N-well and P-well) abut forming a NP junction near a midline. First and second contact regions disposed in device wells are coupled to high and low power sources (I/O pad and ground). Internal isolation regions (shallower STI) extending partially not touching the bottom of surface substrate separate the first and second contact regions. A vertical gate is disposed over the NP junction or over a shallower STI which overlaps the NP junction and separate the second contact regions in x-direction. One or more horizontal gates separate the second contact regions in y-direction and guide the device wells underneath the shallower STI to outer edges to connect with the first contact regions for body contacts. A process for forming the device is also disclosed and is compatible with CMOS processes.Type: GrantFiled: February 29, 2016Date of Patent: February 25, 2020Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Wei Gao, Shaoqiang Zhang, Chien-Hsin Lee
-
Publication number: 20200027826Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to transistor structures and methods of manufacture. The structure includes active metal lines separated by electrically floating metal layers which have a width less than a width of the active metal lines.Type: ApplicationFiled: September 30, 2019Publication date: January 23, 2020Inventors: CHIEN-HSIN LEE, HAOJUN ZHANG, MAHADEVA IYER NATARAJAN
-
Patent number: 10510663Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to transistor structures and methods of manufacture. The structure includes active metal lines separated by electrically floating metal layers which have a width less than a width of the active metal lines.Type: GrantFiled: March 30, 2017Date of Patent: December 17, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Chien-Hsin Lee, Haojun Zhang, Mahadeva Iyer Natarajan
-
Patent number: 10403622Abstract: Structures for a frequency divider, methods of fabricating a frequency divider, and method of using a frequency divider. A first interconnect line is configured to selectively conduct a first signal of a first frequency. A second interconnect line is coupled with the first interconnect line. The second interconnect line is configured to selectively conduct a second signal of a second frequency. The first frequency is less the second frequency.Type: GrantFiled: February 6, 2018Date of Patent: September 3, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Mahadeva Iyer Natarajan, Haojun Zhang, Chien-Hsin Lee
-
Publication number: 20190244954Abstract: Structures for a frequency divider, methods of fabricating a frequency divider, and method of using a frequency divider. A first interconnect line is configured to selectively conduct a first signal of a first frequency. A second interconnect line is coupled with the first interconnect line. The second interconnect line is configured to selectively conduct a second signal of a second frequency. The first frequency is less the second frequency.Type: ApplicationFiled: February 6, 2018Publication date: August 8, 2019Inventors: Mahadeva Iyer Natarajan, Haojun Zhang, Chien-Hsin Lee
-
Patent number: 10373946Abstract: Various embodiments include fin-type field effect transistor (FinFET) structures. In some cases, a FinFET structure includes: a p-type substrate; a silicon-controlled rectifier (SCR) over the p-type substrate, the SCR including: a p-well region and an adjacent n-well region over the substrate; and a negatively charged fin over the p-well region; and a Schottky diode electrically coupled with the SCR, the Schottky diode including a gate in the n-well region, the Schottky diode positioned to mitigate electrostatic discharge (ESD) across the negatively charged fin and the n-well region in response to application of a forward voltage across the gate.Type: GrantFiled: July 18, 2018Date of Patent: August 6, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Chien-Hsin Lee, Mahadeva Iyer Natarajan, Manjunatha Prabhu
-
Patent number: 10211168Abstract: Methods form integrated circuit structures that include a device layer having electronic devices on a substrate, and a multi-layer interconnect structure connected to the device layer. The multi-layer interconnect structure includes alternating insulator layers and wiring layers, power and ground wiring in the wiring layers, non-functional wiring in the wiring layers called dummy fill, and conductive vias extending through the insulator layers. The conductive vias connect the power and ground wiring in the wiring layers to the electronic devices in the device layer. The non-functional wiring is insulated from the power wiring in the wiring layer, and from the electronic devices in the device layer. The conductive vias connect the non-functional wiring (the dummy fill) in the wiring layers through the substrate, or a ground bus, thereby continuously removing static charge that would otherwise accumulate during manufacturing processes.Type: GrantFiled: December 14, 2017Date of Patent: February 19, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Krishna M. Chavali, Chien-Hsin Lee, Mahadeva Iyer Natarajan