Abstract: The present disclosure provides system and method embodiments for synchronizing access to memory between a plurality of modules in a pipelined system. One system embodiment, among others, includes an upstream module and a downstream module that each share one or more locations in memory. The upstream module is configured to receive a command pair having matched identifiers, one half (wait command) of which enables the upstream module to delay access to the memory to avoid read-after-write (RAW) hazard, the other half (signal command) which is passed to the downstream module. The downstream module passes the identifier from the signal command to the upstream module at a time corresponding to the downstream module reaching an idle state, thus ceasing access to the memory. The upstream module, upon determining that the identifier received over a direct connection from the downstream module is from the command pair, accesses the one or more locations in the memory.

Abstract: The present disclosure provides system and method embodiments for synchronizing access to memory between a plurality of modules in a pipelined system. One system embodiment, among others, includes an upstream module and a downstream module that each share one or more locations in memory. The upstream module is configured to receive a command pair having matched identifiers, one half (wait command) of which enables the upstream module to delay access to the memory to avoid read-after-write (RAW) hazard, the other half (signal command) which is passed to the downstream module. The downstream module passes the identifier from the signal command to the upstream module at a time corresponding to the downstream module reaching an idle state, thus ceasing access to the memory. The upstream module, upon determining that the identifier received over a direct connection from the downstream module is from the command pair, accesses the one or more locations in the memory.

Abstract: A method and apparatus for managing power consumption in logic modules without causing power surges. A first and second logic module operate in response to a first and second clock signal, respectively, to carry out a command. When the command arrives, the first logic module begins to operate and indicates that it is busy. After a first delay, the second module begins to operate and indicates that it is busy. When both modules are finished and no new command is available, the busy indicators are deactivated and after a second delay the first clock signal is deactivated. A third delay after the first clock signal is deactivated, the second clock is deactivated. The first, second and third delays are programmable to avoid power surges in the respective modules.

Abstract: A method and apparatus for managing power consumption in logic modules without causing power surges. A first and second logic module operate in response to a first and second clock signal, respectively, to carry out a command. When the command arrives, the first logic module begins to operate and indicates that it is busy. After a first delay, the second module begins to operate and indicates that it is busy. When both modules are finished and no new command is available, the busy indicators are deactivated and after a second delay the first clock signal is deactivated. A third delay after the first clock signal is deactivated, the second clock is deactivated. The first, second and third delays are programmable to avoid power surges in the respective modules.