Patents by Inventor Chih-Chao Yang

Chih-Chao Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • TOP VIA INTERCONNECTS WITH LINE WIGGLING PREVENTION
    Publication number: 20230102662
    Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A metal line is formed on a bottom liner, a sacrificial hardmask on a top surface of the metal line. Portions of the sacrificial hardmask are selectively removed that that do not correspond a desired location of a top via. The remaining sacrificial hardmask is replaced with the top via, the top via and the metal line each tapered such that a width at each respective bottom surface is greater than a width of each respective top surface.
    Type: Application
    Filed: September 28, 2021
    Publication date: March 30, 2023
    Inventors: Tao Li, Ruilong Xie, Tsung-Sheng Kang, Chih-Chao Yang
  • DUAL LAYER TOP CONTACT FOR MAGNETIC TUNNEL JUNCTION STACK
    Publication number: 20230098576
    Abstract: A semiconductor device includes a dual layer top contact upon a MTJ stack. The dual layer top contact includes lower contact and upper contact. The lower contact may be wider and/or shallower relative to the upper contact. This wide and/or shallow geometry of the lower contact may decrease the propensity for over etching, during the formation of the upper contact, opening downward into the MTJ stack and may therefore prevent undesired shorting of the MTJ stack. Further, the lower contact may further protect the MTJ stack even when the upper contact is misaligned to the MTJ stack.
    Type: Application
    Filed: September 26, 2021
    Publication date: March 30, 2023
    Inventors: Ashim Dutta, Chih-Chao Yang
  • MULTI-DIAMETER MAGNETIC RANDOM-ACCESS MEMORY PILLAR STRUCTURE
    Publication number: 20230087231
    Abstract: A semiconductor structure comprises a reference layer of a magnetic random-access memory pillar structure, the reference layer having a first diameter, a free layer of the magnetic random-access memory pillar structure disposed over the reference layer, the free layer having a second diameter, and an electrode layer of the magnetic random-access memory pillar structure disposed over the free layer, the electrode layer having a third diameter. At least two of the first diameter, the second diameter and the third diameter are different.
    Type: Application
    Filed: September 20, 2021
    Publication date: March 23, 2023
    Inventors: Oscar van der Straten, Koichi Motoyama, Joseph F. Maniscalco, Chih-Chao Yang
  • SELF ALIGNED QUADRUPLE PATTERNING INTERCONNECTS
    Publication number: 20230086420
    Abstract: Methods for forming conductive lines and integrated chips include forming a mandrel on an etch stop layer. First spacers are formed on sidewalls of the mandrel. The mandrel is etched away. Conductive lines are formed on sidewalls of the first spacers. The first spacers are etched away. Dielectric spacers are formed between the conductive lines.
    Type: Application
    Filed: September 20, 2021
    Publication date: March 23, 2023
    Inventors: Hsueh-Chung Chen, Chanro Park, Koichi Motoyama, Chih-Chao Yang
  • METAL-INSULATOR-METAL CAPACITOR STRUCTURE SUPPORTING DIFFERENT VOLTAGE APPLICATIONS
    Publication number: 20230088799
    Abstract: A metal-insulator-metal (MIM) capacitor structure includes a substrate extending along a first direction to define a length, a second direction orthogonal to the first direction to define a width, and a third direction orthogonal to the first and second direction to define a height. The substrate includes a first capacitance region and a second capacitance region. The first capacitance region has a first maximum operating voltage (Vmax) and the second capacitance region has a second Vmax that is greater than the first Vmax.
    Type: Application
    Filed: September 23, 2021
    Publication date: March 23, 2023
    Inventors: Baozhen Li, Chih-Chao Yang, Nan Jing, Huimei Zhou
  • BEOL TIP-TO-TIP SHORTING AND TIME DEPENDENT DIELECTRIC BREAKDOWN
    Publication number: 20230090755
    Abstract: A dielectric layer is located on top of and in contact with a substrate. A conductive line located within the dialectic layer. A barrier layer on top of an in contact with the dielectric layer. The barrier layer is below the conductive line. A liner layer on top of and in contact with the barrier layer and below and in contact with the conductive line. A metal liner on top of and in contact with the conductive line. A capping layer on top of and in contact with the dielectric layer, the barrier layer, the liner layer, and the metal liner.
    Type: Application
    Filed: September 21, 2021
    Publication date: March 23, 2023
    Inventors: CHANRO PARK, Koichi Motoyama, Kenneth Chun Kuen Cheng, Chih-Chao Yang
  • DECOUPLED INTERCONNECT STRUCTURES
    Publication number: 20230081953
    Abstract: A semiconductor component includes an insulative layer having a lowermost surface arranged on top of a bottom dielectric material. The semiconductor component further includes a first interconnect structure arranged in the bottom dielectric material such that an uppermost surface of the first interconnect structure is arranged at a first height relative to the lowermost surface of the insulative layer. The semiconductor component further includes a pillar connected to the first interconnect structure and extending through the insulative layer. The semiconductor component further includes a second interconnect structure arranged in the bottom dielectric material such that an uppermost surface of the second interconnect structure is arranged at a second height relative to the lowermost surface of the insulative layer. The second height is different than the first height.
    Type: Application
    Filed: September 14, 2021
    Publication date: March 16, 2023
    Inventors: Saumya Sharma, Ashim Dutta, Tianji Zhou, Chih-Chao Yang
  • BEOL ETCH STOP LAYER WITHOUT CAPACITANCE PENALTY
    Publication number: 20230080438
    Abstract: An etch stop layer is located on top of a first dielectric layer. A conductive line is located on top of the etch stop layer. A second dielectric layer is located above the first dielectric layer. The second dialect layer is in contact with the first dielectric layer.
    Type: Application
    Filed: September 16, 2021
    Publication date: March 16, 2023
    Inventors: CHANRO PARK, Koichi Motoyama, Kenneth Chun Kuen Cheng, Chih-Chao Yang
  • THREE-DIMENSIONAL METAL-INSULATOR-METAL CAPACITOR EMBEDDED IN SEAL STRUCTURE
    Publication number: 20230084798
    Abstract: Embodiments of the present invention are directed to methods and resulting structures for integrated circuits having metal-insulator-metal (MIM) capacitors that serve as both decoupling capacitors and crack stops. In a non-limiting embodiment, an interconnect is formed on a first portion of a substrate in an interior region of the integrated circuit. A second portion of the substrate is exposed in an edge region of the integrated circuit. A MIM capacitor is formed over the second portion of the substrate in the edge region. The MIM capacitor includes two or more plates and one or more dielectric layers. Each dielectric layer is positioned between an adjacent pair of the two or more plates and a portion of the two or more plates extends over the interconnect in the interior region. A plate of the two or more plates is electrically coupled to a last metal wiring level of the interconnect.
    Type: Application
    Filed: September 15, 2021
    Publication date: March 16, 2023
    Inventors: Baozhen Li, Chih-Chao Yang, HUIMEI ZHOU, Nan JING
  • TOP VIA INTERCONNECTS WITHOUT BARRIER METAL BETWEEN VIA AND ABOVE LINE
    Publication number: 20230077760
    Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A high modulus material layer is formed on a conductive stack. A trench is formed that exposes a surface of the liner and filled with metal. The metal is patterned to form interconnect lines and vias. The high modulus material is removed. A conformal layer is formed on exposed surfaces of the stack and the interconnect lines and vias. A low-? dielectric is formed on the conformal layer such that the low-? dielectric is of a height coplanar with the top surface of the vias. The conformal layer is removed from a top surface of the vias. A next level metal layer is formed on the top surface of the vias and low-? dielectric layer such that added vias of the next level metal layer are directly on the top surface of the vias.
    Type: Application
    Filed: September 14, 2021
    Publication date: March 16, 2023
    Inventors: Koichi Motoyama, Kenneth Chun Kuen Cheng, Chanro Park, Chih-Chao Yang
  • Non volatile resistive memory logic device
    Patent number: 11600325
    Abstract: A resistance switching RAM logic device is presented. The device includes a pair of resistance switching RAM cells that may be independently programed into at least a low resistance state (LRS) or a high resistance state (HRS). The resistance switching RAM logic device may further include a shared output node electrically connected to the pair of resistance switching RAM cells. A logical output may be determined from the programmed resistance state of each of the resistance switching RAM cells.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: March 7, 2023
    Assignee: International Business Machines Corporation
    Inventors: Hsueh-Chung Chen, Mary Claire Silvestre, Soon-Cheon Seo, Chi-Chun Liu, Fee Li Lie, Chih-Chao Yang, Yann Mignot, Theodorus E. Standaert
  • REPLACEMENT BOTTOM ELECTRODE STRUCTURE FOR MRAM DEVICES
    Publication number: 20230044333
    Abstract: Memory structures including an MTJ-containing pillar that is void of re-sputtered bottom electrode metal particles is provided by first forming the MTJ-containing pillar on a sacrificial material-containing structure, and thereafter replacing the sacrificial material-containing structure with at least a replacement bottom electrode structure. In some embodiments, the sacrificial material-containing structure is replaced with both a bottom electrode diffusion barrier liner and a replacement bottom electrode structure.
    Type: Application
    Filed: August 4, 2021
    Publication date: February 9, 2023
    Inventors: Oscar van der Straten, Koichi Motoyama, Joseph F. Maniscalco, Chih-Chao Yang
  • SEMICONDUCTOR DEVICE WITH REDUCED VIA RESISTANCE
    Publication number: 20230013937
    Abstract: A semiconductor interconnect structure having a first electrically conductive structure having a plurality of bottom portions; a dielectric capping layer, at least a portion of the dielectric capping layer being in contact with a first bottom portion of the plurality of bottom portions; and a second electrically conductive structure in electrical contact with a second bottom portion of the plurality of bottom portions. A method of forming the interconnect structure is also provided.
    Type: Application
    Filed: September 26, 2022
    Publication date: January 19, 2023
    Inventors: Conal E. Murray, Chih-Chao Yang
  • Electrode with alloy interface
    Patent number: 11557482
    Abstract: An electrode structure with an alloy interface is provided. In one aspect, a method of forming a contact structure includes: patterning a via in a first dielectric layer; depositing a barrier layer onto the first dielectric layer, lining the via; depositing and polishing a first metal layer (Element A) into the via to form a contact in the via; depositing a second metal layer (Element B) onto the contact in the via; annealing the first and second metal layers under conditions sufficient to form an alloy AB; depositing a third metal layer onto the second metal layer; patterning the second and third metal layers into a pedestal stack over the contact to form an electrode over the contact, wherein the alloy AB is present at an interface of the electrode and the contact; and depositing a second dielectric that surrounds the pedestal stack. A contact structure is also provided.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: January 17, 2023
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Daniel Charles Edelstein, Chao-Kun Hu, Oscar van der Straten
  • Via cleaning to reduce resistance
    Patent number: 11557507
    Abstract: A semiconductor structure includes a multilayer structure having a first layer and a second layer disposed on the first layer. The semiconductor structure further includes at least a first via extending from a top of the second layer to a top of a first metal contact disposed in the first layer. A polymer film is disposed on at least a portion of sidewalls of the first via.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: January 17, 2023
    Assignee: International Business Machines Corporation
    Inventors: Yann A. M. Mignot, Chih-Chao Yang
  • VERTICALLY-STACKED INTERDIGITATED METAL-INSULATOR-METAL CAPACITOR FOR SUB-20 NM PITCH
    Publication number: 20220384564
    Abstract: An interdigitated metal-insulator-metal capacitor structure is formed by a first unitary body of a first conductive material that includes a first metal plate, a first set of interdigitated electrodes protruding upwards from a top surface of the first metal plate, and a first set of connecting vias protruding downwards from a bottom surface of the first metal plate. A second unitary body of a second conductive material is disposed above the first unitary body and electrically separated from the first unitary body by an insulating layer. The second unitary body includes a second metal plate, a second set of interdigitated electrodes protruding downwards from a bottom surface of the second metal plate, and a second set of connecting vias protruding upwards from a top surface of the second metal plate. The first set of interdigitated electrodes are interleaved with the second set of interdigitated electrodes.
    Type: Application
    Filed: May 27, 2021
    Publication date: December 1, 2022
    Inventors: Hsueh-Chung Chen, Chih-Chao Yang
  • Aluminum alloy wheel and method for manufacturing the same
    Patent number: 11504763
    Abstract: An aluminum alloy wheel for a vehicle is provided, which includes: a wheel central portion, a rim portion, and a plurality of radial elements, wherein the aluminum alloy wheel is processed by centrifugal casting and forging to form a central portion with a morphology exhibiting a grain size variation with decreasing gradient in a lateral direction from an inner side of the wheel central portion to an outer side thereof.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: November 22, 2022
    Assignee: Industrial Technology Research Institute
    Inventors: Yu-Hsien Chou, Chi-San Chen, Chih-Chao Yang, Chang-Ching Chen
  • MRAM STRUCTURE WITH MULTILAYER ENCAPSULATION
    Publication number: 20220367788
    Abstract: A semiconductor structure may include a pyramidal magnetic tunnel junction on top of a bottom electrode, a tunnel layer on top and in electrical contact with the first magnetic layer, a second magnetic layer on top and in electrical contact with the tunnel layer, and a hard mask cap on top of the second magnetic layer. The pyramidal magnetic tunnel junction may have a first magnetic layer on top and in electrical contact with the bottom electrode. The semiconductor structure may include a first encapsulation spacer positioned along vertical sidewalls of the hard mask cap, a second encapsulation spacer positioned along vertical sidewalls of the second magnetic layer, a third encapsulation spacer positioned along vertical sidewalls of the tunnel layer, and a fourth encapsulation spacer positioned along vertical sidewalls of the first magnetic layer.
    Type: Application
    Filed: May 12, 2021
    Publication date: November 17, 2022
    Inventors: Oscar van der Straten, Koichi Motoyama, Joseph F. Maniscalco, Chih-Chao Yang
  • Embedded memory devices
    Patent number: 11502242
    Abstract: A semiconductor device includes a base structure of an embedded memory device including a bottom electrode contact (BEC) landing pad within a memory area of the embedded memory device and a first metallization level having at least a first conductive line within a logic area of the embedded memory device, a cap layer disposed on the base structure, a BEC disposed through the cap layer on the BEC landing pad, a memory pillar disposed on the BEC and the cap layer, encapsulation layers encapsulating the memory pillar to protect the memory stack, and a second metallization level including a second conductive line surrounding the top electrode, a via disposed on the first conductive line such that the second via is below the top electrode, and a third conductive line disposed on the via to enable the memory pillar to be fitted between the first and second metallization levels.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: November 15, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ashim Dutta, Chih-Chao Yang, Michael Rizzolo, Theodorus E. Standaert
  • HIGH-DENSITY MEMORY DEVICES USING OXIDE GAP FILL
    Publication number: 20220359814
    Abstract: A semiconductor structure forms two or more tightly pitched memory devices using a dielectric material for a gap fill material. The approach includes providing two adjacent bottom electrodes in a layer of an insulating material and above a metal layer. Two adjacent pillars are each above one of the two adjacent bottom electrodes where each pillar of the two adjacent pillars is composed of a stack of materials for a memory device. A spacer is around the vertical sides each of the two adjacent pillars. The dielectric material is on the spacer around the vertical sides each of the two adjacent pillars, on the layer of the insulating material between the two adjacent bottom electrodes. The dielectric material fills at least a first portion of a gap between the two adjacent pillars. A low k material covers the dielectric material and exposed portions of the layer of the insulating material.
    Type: Application
    Filed: May 6, 2021
    Publication date: November 10, 2022
    Inventors: Theodorus E. Standaert, Daniel Charles Edelstein, Chih-Chao Yang