Patents by Inventor Chih-Chi Lin
Chih-Chi Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11982866Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.Type: GrantFiled: December 15, 2022Date of Patent: May 14, 2024Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Liang-Ting Ho, Chen-Er Hsu, Yi-Liang Chan, Fu-Lai Tseng, Fu-Yuan Wu, Chen-Chi Kuo, Ying-Jen Wang, Wei-Han Hsia, Yi-Hsin Tseng, Wen-Chang Lin, Chun-Chia Liao, Shou-Jen Liu, Chao-Chun Chang, Yi-Chieh Lin, Shang-Yu Hsu, Yu-Huai Liao, Shih-Wei Hung, Sin-Hong Lin, Kun-Shih Lin, Yu-Cheng Lin, Wen-Yen Huang, Wei-Jhe Shen, Chih-Shiang Wu, Sin-Jhong Song, Che-Hsiang Chiu, Sheng-Chang Lin
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Publication number: 20240146205Abstract: A flyback power converter includes a power transformer, a first lossless voltage conversion circuit, a first low-dropout linear regulator and a secondary side power supply circuit. The first low-dropout linear regulator (LDO) generates a first operation voltage as power supply for being supplied to a sub-operation circuit. The secondary side power supply circuit includes a second lossless voltage conversion circuit and a second LDO. The second LDO generates a second operation voltage. The first operation voltage and the second operation voltage are shunted to a common node. When a first lossless conversion voltage is greater than a first threshold voltage, the second LDO is enabled to generate the second operation voltage to replace the first operation voltage as power supply supplied to the sub-operation circuit; wherein the second lossless conversion voltage is lower than the first lossless switching voltage.Type: ApplicationFiled: September 23, 2023Publication date: May 2, 2024Inventors: Shin-Li Lin, He-Yi Shu, Shih-Jen Yang, Ta-Yung Yang, Yi-Min Shiu, Chih-Ching Lee, Yu-Chieh Hsieh, Chao-Chi Chen
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Patent number: 11966133Abstract: An electronic device is disclosed. The electronic device includes a substrate, a plurality of color filters disposed on the substrate, an optical film disposed on the plurality of color filter, and a defect disposed between the substrate and the optical film. The optical film has a first base, a protective layer on the first base, and a second base between the first base and the protective layer and having a first processed area. In a top view of the electronic device, the first processed area corresponds to the defect and at least partially overlaps at least two color filters.Type: GrantFiled: May 18, 2023Date of Patent: April 23, 2024Assignee: INNOLUX CORPORATIONInventors: Tai-Chi Pan, Chin-Lung Ting, I-Chang Liang, Chih-Chiang Chang Chien, Po-Wen Lin, Kuang-Ming Fan, Sheng-Nan Chen
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Patent number: 11955515Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.Type: GrantFiled: July 28, 2022Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Chuan Chiu, Chia-Hao Chang, Cheng-Chi Chuang, Chih-Hao Wang, Huan-Chieh Su, Chun-Yuan Chen, Li-Zhen Yu, Yu-Ming Lin
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Patent number: 11942750Abstract: A laser inspection system is provided. A laser source emits a laser with a first spectrum and the laser is transmitted by a first optical fiber. A gain optical fiber doped with special ions is connected to the first optical fiber, and a light detector is provided around the gain optical fiber. When the laser with the first spectrum passes through the gain optical fiber, the gain optical fiber absorbs part of the energy level of the laser with the first spectrum, so that the laser with the first spectrum is converted to generate light with a second spectrum based on the frequency conversion phenomenon. The light detector detects the intensity of the light with the second spectrum, so that the power of the laser source can be obtained.Type: GrantFiled: November 23, 2020Date of Patent: March 26, 2024Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yi-Chi Lee, Hsin-Chia Su, Shih-Ting Lin, Yu-Cheng Song, Fu-Shun Ho, Chih-Chun Chen
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Publication number: 20240096958Abstract: An embodiment is a semiconductor structure. The semiconductor structure includes a fin on a substrate. A gate structure is over the fin. A source/drain is in the fin proximate the gate structure. The source/drain includes a bottom layer, a supportive layer over the bottom layer, and a top layer over the supportive layer. The supportive layer has a different property than the bottom layer and the top layer, such as a different material, a different natural lattice constant, a different dopant concentration, and/or a different alloy percent content.Type: ApplicationFiled: November 28, 2023Publication date: March 21, 2024Inventors: Jung-Chi Tai, Chii-Horng Li, Pei-Ren Jeng, Yen-Ru Lee, Yan-Ting Lin, Chih-Yun Chin
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Patent number: 11935825Abstract: An IC structure includes a fin structure, a contact overlying the fin structure along a first direction, and an isolation layer between the contact and the fin structure. The isolation layer is adjacent to a portion of the contact along a second direction perpendicular to the first direction.Type: GrantFiled: August 28, 2019Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kam-Tou Sio, Cheng-Chi Chuang, Chih-Ming Lai, Jiann-Tyng Tzeng, Wei-Cheng Lin, Lipen Yuan
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Patent number: 11935794Abstract: A method of forming a semiconductor transistor device. The method comprises forming a channel structure over a substrate and forming a first source/drain structure and a second source/drain structure on opposite sides of the fin structure. The method further comprises forming a gate structure surrounding the fin structure. The method further comprises flipping and partially removing the substrate to form a back-side capping trench while leaving a lower portion of the substrate along upper sidewalls of the first source/drain structure and the second source/drain structure as a protective spacer. The method further comprises forming a back-side dielectric cap in the back-side capping trench.Type: GrantFiled: December 12, 2022Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Huan-Chieh Su, Cheng-Chi Chuang, Chih-Hao Wang, Zhi-Chang Lin, Li-Zhen Yu
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Publication number: 20240087949Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a substrate. A gate electrode is over the substrate and a spacer structure laterally surrounds the gate electrode. A conductive via is disposed on the gate electrode. A liner is arranged along one or more sidewalls of the spacer structure. The conductive via has a bottommost surface that has a larger width than a part of the conductive via that is laterally adjacent to one or more interior sidewalls of the liner.Type: ApplicationFiled: November 16, 2023Publication date: March 14, 2024Inventors: Li-Zhen Yu, Cheng-Chi Chuang, Chih-Hao Wang, Yu-Ming Lin, Lin-Yu Huang
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Patent number: 11920190Abstract: Methods of amplifying and determining a target nucleotide sequence are provided. The method of amplifying the target nucleotide sequence includes the following steps. A first adaptor and a second adaptor are linked to two ends of a double-stranded nucleic acid molecule with a target nucleotide sequence respectively to form a nucleic acid template, in which the first adaptor includes a Y-form adaptor or a hairpin adaptor and the second adaptor is a hairpin adaptor. Then, a PCR amplification cycle is performed on the nucleic acid template to obtain a PCR amplicon of the target nucleotide sequence.Type: GrantFiled: December 28, 2020Date of Patent: March 5, 2024Assignee: Industrial Technology Research InstituteInventors: Pei-Shin Jiang, Jenn-Yeh Fann, Hung-Chi Chien, Yu-Yu Lin, Chih-Lung Lin
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Patent number: 11916077Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.Type: GrantFiled: May 24, 2021Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Ru-Gun Liu, Wei-Cheng Lin, Lei-Chun Chou, Wei-An Lai
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Patent number: 11915977Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers.Type: GrantFiled: April 12, 2021Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Ting Tsai, Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Chih-Hui Huang, Sheng-Chau Chen, Shih Pei Chou, Chia-Chieh Lin
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Patent number: 11154984Abstract: A robot mechanism is provided, including a base, a main body, a motor, a driver, a bottom plate, a flexible heat conductive member, and a controller. The main body is connected to the base and has a housing. The motor and the driver are disposed in the main body, and the driver is electrically connected to the motor. The bottom plate is disposed on the housing and situated between the driver and the housing, and a gap is formed between the bottom plate and the driver. The flexible heat conductive member is disposed between the driver and the housing. The flexible heat conductive member contacts the driver. The controller is detachably disposed in the base.Type: GrantFiled: June 10, 2019Date of Patent: October 26, 2021Assignee: DELTA ELECTRONICS, INC.Inventors: Chi-Jung Huang, Chih-Cheng Peng, Tzu-Min Yi, Chih-Chi Lin
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Publication number: 20200180147Abstract: A robot mechanism is provided, including a base, a main body, a motor, a driver, a bottom plate, a flexible heat conductive member, and a controller. The main body is connected to the base and has a housing. The motor and the driver are disposed in the main body, and the driver is electrically connected to the motor. The bottom plate is disposed on the housing and situated between the driver and the housing, and a gap is formed between the bottom plate and the driver. The flexible heat conductive member is disposed between the driver and the housing. The flexible heat conductive member contacts the driver. The controller is detachably disposed in the base.Type: ApplicationFiled: June 10, 2019Publication date: June 11, 2020Inventors: Chi-Jung HUANG, Chih-Cheng PENG, Tzu-Min YI, Chih-Chi LIN
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Patent number: 9887773Abstract: A wavelength division multiplexing (WDM) transistor-outline (TO)-can assembly is provided that is capable of transmitting optical data signals having multiple wavelengths. The WDM TO-can assembly can be packaged in a relatively small package without requiring a large amount of plant retooling or capital investment, and that can be made available in the market relatively quickly. A plurality of the WDM TO-can assemblies can be incorporated into a small form factor or C form factor pluggable-type optical communications module to achieve high data rates.Type: GrantFiled: September 19, 2016Date of Patent: February 6, 2018Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Kou-Wei Wang, Ayman Kanan, Chih-Chi Lin
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Patent number: 9784919Abstract: Wavelength division multiplexing and demultiplexing (WDM) TOSA and ROSA TO-can assemblies are provided that are capable of transmitting and receiving optical data signals, respectively, having more than three wavelengths, that can be packaged in smaller packages than those used for existing BOSAs and tri-OSAs, that can be manufactured without requiring a large amount of plant retooling or capital investment, and that can be made available in the market relatively quickly.Type: GrantFiled: September 30, 2015Date of Patent: October 10, 2017Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.Inventors: Kou-Wei Wang, Chih-Chi Lin, Ching-Jung Li, Chihhsien Chang, Tien-Tsorng Shih, Yao-Chien Chuang
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Publication number: 20170093488Abstract: A wavelength division multiplexing (WDM) transistor-outline (TO)-can assembly is provided that is capable of transmitting optical data signals having multiple wavelengths. The WDM TO-can assembly can be packaged in a relatively small package without requiring a large amount of plant retooling or capital investment, and that can be made available in the market relatively quickly. A plurality of the WDM TO-can assemblies can be incorporated into a small form factor or C form factor pluggable-type optical communications module to achieve high data rates.Type: ApplicationFiled: September 19, 2016Publication date: March 30, 2017Inventors: Kou-Wei Wang, Ayman Kanan, Chih-Chi Lin
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Publication number: 20170090121Abstract: Wavelength division multiplexing and demultiplexing (WDM) TOSA and ROSA TO-can assemblies are provided that are capable of transmitting and receiving optical data signals, respectively, having more than three wavelengths, that can be packaged in smaller packages than those used for existing BOSAs and tri-OSAs, that can be manufactured without requiring a large amount of plant retooling or capital investment, and that can be made available in the market relatively quickly.Type: ApplicationFiled: September 30, 2015Publication date: March 30, 2017Inventors: Kou-Wei Wang, Chih-Chi Lin, Ching-Jung LI, Chihhsien Chang, Tien-Tsorng Shih, Yao-Chien Chuang
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Patent number: D911409Type: GrantFiled: January 15, 2020Date of Patent: February 23, 2021Assignee: DELTA ELECTRONICS, INC.Inventors: Min-Min Ou Yang, Chih-Chi Lin, Po-Yen Tseng