Patents by Inventor Chih-Chia Hsu
Chih-Chia Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11982866Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.Type: GrantFiled: December 15, 2022Date of Patent: May 14, 2024Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Liang-Ting Ho, Chen-Er Hsu, Yi-Liang Chan, Fu-Lai Tseng, Fu-Yuan Wu, Chen-Chi Kuo, Ying-Jen Wang, Wei-Han Hsia, Yi-Hsin Tseng, Wen-Chang Lin, Chun-Chia Liao, Shou-Jen Liu, Chao-Chun Chang, Yi-Chieh Lin, Shang-Yu Hsu, Yu-Huai Liao, Shih-Wei Hung, Sin-Hong Lin, Kun-Shih Lin, Yu-Cheng Lin, Wen-Yen Huang, Wei-Jhe Shen, Chih-Shiang Wu, Sin-Jhong Song, Che-Hsiang Chiu, Sheng-Chang Lin
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Patent number: 11985324Abstract: Exemplary video processing methods and apparatuses for encoding or decoding a current block by inter prediction are disclosed. Input data of a current block is received and partitioned into sub-partitions and motion refinement is independently performed on each sub-partition. A reference block for each sub-partition is obtained from one or more reference pictures according to an initial motion vector (MV). A refined MV for each sub-partition is derived by searching around the initial MV with N-pixel refinement. One or more boundary pixels of the reference block for a sub-partition is padded for motion compensation of the sub-partition. A final predictor for the current block is generated by performing motion compensation for each sub-partition according to its refined MV. The current block is then encoded or decoded according to the final predictor.Type: GrantFiled: March 13, 2020Date of Patent: May 14, 2024Assignee: HFI INNOVATION INC.Inventors: Yu-Cheng Lin, Chun-Chia Chen, Chih-Wei Hsu, Ching-Yeh Chen, Tzu-Der Chuang, Yu-Wen Huang
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Patent number: 11979593Abstract: Method and apparatus for affine CPMV or ALF refinement are mentioned. According to this method, statistical data associated with the affine CPMV or ALF refinement are collected over a picture area. Updated parameters for the affine CPMV refinement or the ALF refinement are then derived based on the statistical data, where a process to derive the updated parameters includes performing multiplication using a reduced-precision multiplier for the statistical data. The reduced-precision multiplier truncates at least one bit of the mantissa part. In another embodiment, the process to derive the updated parameters includes performing reciprocal for the statistical data using a lookup table with (m?k)-bit input by truncating k bits from the m-bit mantissa part, and contents of the lookup table includes m-bit outputs. m and k are positive integers.Type: GrantFiled: April 25, 2022Date of Patent: May 7, 2024Assignee: MEDIATEK INC.Inventors: Shih-Chun Chiu, Tzu-Der Chuang, Ching-Yeh Chen, Chun-Chia Chen, Chih-Wei Hsu, Yu-Wen Huang
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Patent number: 11973985Abstract: Various schemes pertaining to pre-encoding processing of a video stream with motion compensated temporal filtering (MCTF) are described. An apparatus determines a filtering interval for a received raw video stream having pictures in a temporal sequence. The apparatus selects from the pictures a plurality of target pictures based on the filtering interval, as well as a group of reference pictures for each target picture to perform pixel-based MCTF, which generates a corresponding filtered picture for each target picture. The apparatus subsequently transmits the filtered pictures as well as non-target pictures to an encoder for encoding the video stream. Subpictures of natural images and screen content images are separately processed by the apparatus.Type: GrantFiled: August 22, 2022Date of Patent: April 30, 2024Assignee: MediaTek Inc.Inventors: Chih-Yao Chiu, Chun-Chia Chen, Chih-Wei Hsu, Tzu-Der Chuang, Ching-Yeh Chen, Yu-Wen Huang
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Patent number: 11943584Abstract: A micro-electro-mechanical system (MEMS) microphone is provided. The MEMS microphone includes a substrate, a diaphragm, a backplate and a first protrusion. The substrate has an opening portion. The diaphragm is disposed on one side of the substrate and extends across the opening portion of the substrate. The backplate includes a plurality of acoustic holes. The backplate is disposed on one side of the diaphragm. An air gap is formed between the backplate and the diaphragm. The first protrusion extends from the backplate towards the air gap.Type: GrantFiled: April 7, 2022Date of Patent: March 26, 2024Assignee: FORTEMEDIA, INC.Inventors: Chih-Yuan Chen, Jien-Ming Chen, Feng-Chia Hsu, Wen-Shan Lin, Nai-Hao Kuo
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Patent number: 11942550Abstract: A method for manufacturing a nanosheet semiconductor device includes forming a poly gate on a nanosheet stack which includes at least one first nanosheet and at least one second nanosheet alternating with the at least one first nanosheet; recessing the nanosheet stack to form a source/drain recess proximate to the poly gate; forming an inner spacer laterally covering the at least one first nanosheet; and selectively etching the at least one second nanosheet.Type: GrantFiled: February 24, 2021Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chien-Chang Su, Yan-Ting Lin, Chien-Wei Lee, Bang-Ting Yan, Chih Teng Hsu, Chih-Chiang Chang, Chien-I Kuo, Chii-Horng Li, Yee-Chia Yeo
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Publication number: 20240096873Abstract: Electrostatic discharge (ESD) structures are provided. An ESD structure includes a semiconductor substrate, a first epitaxy region with a first type of conductivity over the semiconductor substrate, a second epitaxy region with a second type of conductivity over the semiconductor substrate, and a plurality of semiconductor layers. The semiconductor layers are stacked over the semiconductor substrate and between the first and second epitaxy regions. A first conductive feature is formed over the first epitaxy region and outside an oxide diffusion region. A second conductive feature is formed over the second epitaxy region and outside the oxide diffusion region. A third conductive feature is formed over the first epitaxy region and within the oxide diffusion region. A fourth conductive feature is formed over the second epitaxy region and within the oxide diffusion region. The oxide diffusion region is disposed between the first and second conductive features.Type: ApplicationFiled: November 28, 2023Publication date: March 21, 2024Inventors: Chun-Chia HSU, Tung-Heng HSIEH, Yung-Feng CHANG, Bao-Ru YOUNG, Jam-Wem LEE, Chih-Hung WANG
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Patent number: 9899513Abstract: A lateral diffused metal oxide semiconductor (LDMOS) transistor and a manufacturing method thereof are provided. A deep well region is disposed in a substrate. An isolation structure is disposed in the substrate to define a first active area and a second active area. A well region is disposed in the deep well region in the first active area. A gate is disposed on the substrate in the first active area. A gate dielectric layer is disposed between the gate and the substrate. A first doped region is disposed in the well region in the first active area and located at one side of the gate. A second doped region is disposed in the deep well region in the second active area. A conductive structure is disposed on the isolation structure, surrounds the second doped region and is connected to the gate.Type: GrantFiled: December 29, 2016Date of Patent: February 20, 2018Assignee: MACRONIX International Co., Ltd.Inventors: Wei-Chih Lin, Chih-Chia Hsu, Yin-Fu Huang
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Patent number: 9202862Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a first well, a first heavily doping region, a field oxide, a first dielectric layer, and a conductive layer. The first well is disposed on the substrate, and the first heavily doping region is disposed in the first well. The field oxide is disposed on the first well and adjacent to the first heavily doping region. The first dielectric layer is disposed on the field oxide and covering the field oxide. The conductive layer is disposed on the first dielectric layer. The first well and the first heavily doping region have a first type doping.Type: GrantFiled: March 14, 2014Date of Patent: December 1, 2015Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Ming-Tung Lee, Cheng-Chi Lin, Chih-Chia Hsu, Chien-Chung Chen, Shih-Chin Lien, Shyi-Yuan Wu
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Publication number: 20150263085Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a first well, a first heavily doping region, a field oxide, a first dielectric layer, and a conductive layer. The first well is disposed on the substrate, and the first heavily doping region is disposed in the first well. The field oxide is disposed on the first well and adjacent to the first heavily doping region. The first dielectric layer is disposed on the field oxide and covering the field oxide. The conductive layer is disposed on the first dielectric layer. The first well and the first heavily doping region have a first type doping.Type: ApplicationFiled: March 14, 2014Publication date: September 17, 2015Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Ming-Tung Lee, Cheng-Chi Lin, Chih-Chia Hsu, Chien-Chung Chen, Shih-Chin Lien, Shyi-Yuan Wu
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Patent number: 9082787Abstract: A semiconductor structure includes a substrate having a first conductive type, a well having a second conductive type formed in the substrate, a first doped region and a second doped region formed in the well, a field oxide, a first dielectric layer and a second dielectric layer. The field oxide is formed on a surface region of the well and between the first doped region and the second doped region. The first dielectric layer is formed on the surface region of the well and covers an edge portion of the field oxide. The first dielectric layer has a first thickness. The second dielectric layer is formed on the surface region of the well. The second dielectric layer has a second thickness smaller than the first thickness.Type: GrantFiled: December 23, 2013Date of Patent: July 14, 2015Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Yu-Hsien Chin, Chih-Chia Hsu, Yin-Fu Huang
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Patent number: 9029947Abstract: A field device and method of operating high voltage semiconductor device applied with the same are provided. The field device includes a first well having a second conductive type and second well having a first conductive type both formed in the substrate (having the first conductive type) and extending down from a surface of the substrate, the second well adjacent to one side of the first well and the substrate is at the other side of the first well; a first doping region having the first conductive type and formed in the second well, the first doping region spaced apart from the first well; a conductive line electrically connected to the first doping region and across the first well region; and a conductive body insulatively positioned between the conductive line and the first well, and the conductive body correspondingly across the first well region.Type: GrantFiled: October 21, 2014Date of Patent: May 12, 2015Assignee: Macronix International Co., Ltd.Inventors: An-Li Cheng, Miao-Chun Chung, Chih-Chia Hsu, Yin-Fu Huang
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Publication number: 20150035583Abstract: A field device and method of operating high voltage semiconductor device applied with the same are provided. The field device includes a first well having a second conductive type and second well having a first conductive type both formed in the substrate (having the first conductive type) and extending down from a surface of the substrate, the second well adjacent to one side of the first well and the substrate is at the other side of the first well; a first doping region having the first conductive type and formed in the second well, the first doping region spaced apart from the first well; a conductive line electrically connected to the first doping region and across the first well region; and a conductive body insulatively positioned between the conductive line and the first well, and the conductive body correspondingly across the first well region.Type: ApplicationFiled: October 21, 2014Publication date: February 5, 2015Inventors: An-Li Cheng, Miao-Chun Chung, Chih-Chia Hsu, Yin-Fu Huang
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Patent number: 8896061Abstract: A field device and method of operating high voltage semiconductor device applied with the same are provided. The field device includes a first well having a second conductive type and second well having a first conductive type both formed in the substrate (having the first conductive type) and extending down from a surface of the substrate, the second well adjacent to one side of the first well and the substrate is at the other side of the first well; a first doping region having the first conductive type and formed in the second well, the first doping region spaced apart from the first well; a conductive line electrically connected to the first doping region and across the first well region; and a conductive body insulatively positioned between the conductive line and the first well, and the conductive body correspondingly across the first well region.Type: GrantFiled: September 14, 2012Date of Patent: November 25, 2014Assignee: Macronix International Co., Ltd.Inventors: An-Li Cheng, Miao-Chun Chung, Chih-Chia Hsu, Yin-Fu Huang
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Publication number: 20140106519Abstract: A semiconductor structure includes a substrate having a first conductive type, a well having a second conductive type formed in the substrate, a first doped region and a second doped region formed in the well, a field oxide, a first dielectric layer and a second dielectric layer. The field oxide is formed on a surface region of the well and between the first doped region and the second doped region. The first dielectric layer is formed on the surface region of the well and covers an edge portion of the field oxide. The first dielectric layer has a first thickness. The second dielectric layer is formed on the surface region of the well. The second dielectric layer has a second thickness smaller than the first thickness.Type: ApplicationFiled: December 23, 2013Publication date: April 17, 2014Applicant: Macronix International Co., Ltd.Inventors: Yu-Hsien Chin, Chih-Chia Hsu, Yin-Fu Huang
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Patent number: 8691653Abstract: A semiconductor structure and a manufacturing process thereof are disclosed. The semiconductor structure includes a substrate having a first conductive type, a first well having a second conductive type formed in the substrate, a doped region having the second conductive type formed in the first well, a field oxide and a second well having the first conductive type. The doped region has a first net dopant concentration. The field oxide is formed on a surface area of the first well. The second well is disposed underneath the field oxide and connected to a side of the doped region. The second well has a second net dopant concentration smaller than the first net dopant concentration.Type: GrantFiled: March 5, 2012Date of Patent: April 8, 2014Assignee: Macronix International Co., Ltd.Inventors: Chih-Chia Hsu, Yu-Hsien Chin, Yin-Fu Huang
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Publication number: 20140077866Abstract: A field device and method of operating high voltage semiconductor device applied with the same are provided. The field device includes a first well having a second conductive type and second well having a first conductive type both formed in the substrate (having the first conductive type) and extending down from a surface of the substrate, the second well adjacent to one side of the first well and the substrate is at the other side of the first well; a first doping region having the first conductive type and formed in the second well, the first doping region spaced apart from the first well; a conductive line electrically connected to the first doping region and across the first well region; and a conductive body insulatively positioned between the conductive line and the first well, and the conductive body correspondingly across the first well region.Type: ApplicationFiled: September 14, 2012Publication date: March 20, 2014Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: An-Li Cheng, Miao-Chun Chung, Chih-Chia Hsu, Yin-Fu Huang
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Patent number: 8659080Abstract: A semiconductor structure includes a substrate having a first conductive type, a well having a second conductive type formed in the substrate, a first doped region and a second doped region formed in the well, a field oxide, a first dielectric layer and a second dielectric layer. The field oxide is formed on a surface region of the well and between the first doped region and the second doped region. The first dielectric layer is formed on the surface region of the well and covers an edge portion of the field oxide. The first dielectric layer has a first thickness. The second dielectric layer is formed on the surface region of the well. The second dielectric layer has a second thickness smaller than the first thickness.Type: GrantFiled: March 5, 2012Date of Patent: February 25, 2014Assignee: Macronix International Co., Ltd.Inventors: Yu-Hsien Chin, Chih-Chia Hsu, Yin-Fu Huang
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Patent number: 8586442Abstract: A manufacturing method for a high voltage transistor includes the following steps. A substrate is provided. A P-type epitaxial (P-epi) layer is provided above the substrate. An N-well is formed in the P-epi layer. A P-well is formed in the P-epi layer. Field oxide (FOX) layers are formed above the P-epi layer. A gate oxide (GOX) layer is formed between the FOX layers. P-type implants are doped into the P-well or N-type implants are doped into the N-well to adjust an electrical function of the high voltage transistor.Type: GrantFiled: November 28, 2012Date of Patent: November 19, 2013Assignee: Macronix International Co. Ltd.Inventors: Yu-Hsien Chin, Chih-Chia Hsu, Yin-Fu Huang
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Publication number: 20130228861Abstract: A semiconductor structure and a manufacturing process thereof are disclosed. The semiconductor structure includes a substrate having a first conductive type, a first well having a second conductive type formed in the substrate, a doped region having the second conductive type formed in the first well, a field oxide and a second well having the first conductive type. The doped region has a first net dopant concentration. The field oxide is formed on a surface area of the first well. The second well is disposed underneath the field oxide and connected to a side of the doped region. The second well has a second net dopant concentration smaller than the first net dopant concentration.Type: ApplicationFiled: March 5, 2012Publication date: September 5, 2013Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chih-Chia Hsu, Yu-Hsien Chin, Yin-Fu Huang