Patents by Inventor Chih-Chiang Hsu

Chih-Chiang Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090058101
    Abstract: A folding electronic device includes a cover and a main body. The cover includes a groove. The main body includes an engaging structure. The engaging structure includes a pushing element, an elastic element connected to the pushing element, an engaging element and a base. The engaging element includes a first connector and an engaging portion. The first connector is disposed on two sides of the engaging portions. The engaging portion is connected to or is detached from the groove. The base comprises an accommodating portion and a second connector. The pushing element and the elastic element are disposed in the accommodating portion. The second connector is disposed on two sides of the base. The engaging element is installed across the base. The first connector pivots on the second connector.
    Type: Application
    Filed: January 7, 2008
    Publication date: March 5, 2009
    Applicant: QUANTA COMPUTER INC.
    Inventors: Chih-Chiang Hsu, Wen-Chi Huang
  • Publication number: 20090059482
    Abstract: An electronic device comprises a battery and a main body. The battery comprises an engaging element. The engaging element comprises a hook, a depressed surface and an inclined surface. The hook protrudes from the battery. The inclined surface and the depressed surface are connected to two sides of the hook. The main body comprises a linkage. The linkage is slidably disposed on the main body. The linkage comprises a hole with two side walls. The hook is engaged with the hole.
    Type: Application
    Filed: January 7, 2008
    Publication date: March 5, 2009
    Applicant: QUANTA COMPUTER INC.
    Inventors: Chih-Chiang Hsu, Tsung-Ju Chiang
  • Publication number: 20090049333
    Abstract: A built-in redundancy analyzer and a redundancy analysis method thereof for a chip having a plurality of repairable memories are provided. The method includes the following steps. First, the identification code of a repairable memory containing a fault (“fault memory” for short) is identified and a parameter is provided according to the identification code. The parameter includes the length of row address, the length of column address, the length of word, the number of redundancy rows, and the number of redundancy columns of the fault memory. Since the parameter of every individual repairable memory is different, the fault location is converted into a general format according to the parameter for easier processing. A redundancy analysis is then performed according to the parameter and the converted fault location, and the analysis result is converted from the general format to the format of the fault memory and output to the fault memory.
    Type: Application
    Filed: August 13, 2007
    Publication date: February 19, 2009
    Applicant: Faraday Technology Corp.
    Inventors: Tsu-Wei Tseng, Chih-Chiang Hsu, Jin-Fu Li, Chien-Yuan Pao
  • Publication number: 20080124189
    Abstract: The invention provides a connection structure installed in a data processing apparatus. The data processing apparatus includes a keyboard and a base. The keyboard includes a bottom. The base includes a top plate. The connection structure connects the bottom and the top plate. The connection structure includes a mounted boss and a mounting hole. The mounted boss is disposed on the bottom of the keyboard. The mounted boss includes a groove. The mounting hole is disposed on the top plate of the base. The mounting hole includes a protrusion. When the bottom of the keyboard is assembled to the top of the base, the mounted boss would fit into the mounting hole, such that the protrusion is locked with the groove.
    Type: Application
    Filed: October 10, 2007
    Publication date: May 29, 2008
    Inventors: Chih Chiang Hsu, Chia Cheng Tang, Chien Jung Su
  • Patent number: 7356683
    Abstract: A system for monitoring BIOS (Basic Input/Output System) messages of remote computers by a local server includes: the local server (1) for executing a monitoring program (11) to send requests for acquiring BIOS messages, and receive and display the BIOS messages; the remote computers (2), each remote computer executing a POST (Power On Self Test) program for outputting the BIOS messages, receiving a request for acquiring the BIOS messages from the local server, and transmitting the BIOS messages to the local server; and a network (3) for connecting the local server with the remote computers. Each remote computer includes a CPU (Central Processing Unit) (21) for executing the POST program and outputting the BIOS messages, a remote control card (22) for detecting and capturing the BIOS messages, and a PCI (Peripheral Component Interconnect) bus (23) for connecting the CPU with the remote control card. Related methods are also provided.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: April 8, 2008
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Chih-Chiang Hsu