Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes an interconnect dielectric layer over a substrate. An interconnect via is within the interconnect dielectric layer, and an interconnect wire is over the interconnect via and within the interconnect dielectric layer. A protective layer surrounds the interconnect via. The interconnect via vertically extends through the protective layer to below a bottom of the protective layer. The protective layer continuously extends from along an outer sidewall of the interconnect via to along an outer sidewall of the interconnect wire in a first cross-sectional view.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: The present disclosure provides a circuitry. The circuitry includes a comparator and a signal correlated circuit. The comparator includes a first input terminal, a second input terminal, and an output terminal. The signal correlated circuit includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal is coupled to receive a first input signal. The second input terminal is coupled to receive a second input signal independent from the first input signal. The first output terminal is configured to generate a first output signal and to send the first output signal to the first input terminal of the comparator. The second output terminal is configured to generate a second output signal and to send the second output signal to the second input terminal of the comparator. The first output signal and the second output signal are correlated.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer arranged over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a barrier structure is arranged directly over the interconnect wire. The integrated chip further includes an etch stop layer arranged over the barrier structure and surrounds outer sidewalls of the barrier structure. A second interconnect dielectric layer is arranged over the etch stop layer, and an interconnect via extends through the second interconnect dielectric layer, the etch stop layer, and the barrier structure to contact the interconnect wire.

Abstract: A method of forming a semiconductor device structure is provided. The method includes forming a masking structure with first openings over a semiconductor substrate and correspondingly forming metal layers in the first openings. The method also includes recessing the masking structure to form second openings between the metal layers and forming a sacrificial layer surrounded by a first liner in each of the second openings. In addition, after forming a second liner over the sacrificial layer in each of the second openings, the method includes removing the sacrificial layer in each of the second openings to form a plurality of air gaps therefrom.

Abstract: A liquid storage tank includes a housing, a piston located in the housing, a cover, an elastic element, and an outlet pipe. The cover is attached to the housing and has a support post extending toward the piston. The piston, the housing, and the cover define a tank chamber. The tank chamber is filled with cooling liquid. The elastic element is connected with the tank hosing and the piston. The elastic element is free from contact with the cooling liquid. The outlet pipe communicates with the tank chamber. An extension direction of an opening of the outlet pipe is not parallel to a direction of movement of the elastic element. When the cooling liquid is decreased, the piston compressed the tank chamber such that the elastic element is released. The tank chamber is continuously compressed by pairing the elastic element and the piston.

Abstract: A memory cell includes a transistor over a semiconductor substrate. The transistor includes a ferroelectric layer arranged along a sidewall of a word line. The ferroelectric layer includes a species with valence of 5, valence of 7, or a combination thereof. An oxide semiconductor layer is electrically coupled to a source line and a bit line. The ferroelectric layer is disposed between the oxide semiconductor layer and the word line.

Abstract: An antiferroelectric field effect transistor (Anti-FeFET) of a memory cell includes an antiferroelectric layer instead of a ferroelectric layer. The antiferroelectric layer may operate based on a programmed state and an erased state in which the antiferroelectric layer is in a fully polarized alignment and a non-polarized alignment (or a random state of polarization), respectively. This enables the antiferroelectric layer in the FeFET to provide a sharper/larger voltage drop for an erase operation of the FeFET (e.g., in which the FeFET switches or transitions from the programmed state to the erased state) relative to a ferroelectric material layer that operates based on switching between two opposing fully polarized states.

Abstract: In some embodiments, the present disclosure relates to a method of forming an interconnect. The method includes forming an etch stop layer (ESL) over a lower conductive structure and forming one or more dielectric layers over the ESL. A first patterning process is performed on the one or more dielectric layers to form interconnect opening and a second patterning process is performed on the one or more dielectric layers to increase a depth of the interconnect opening and expose an upper surface of the ESL. A protective layer is selectively formed on sidewalls of the one or more dielectric layers forming the interconnect opening. A third patterning process is performed to remove portions of the ESL that are uncovered by the one or more dielectric layers and the protective layer and to expose the lower conductive structure. A conductive material is formed within the interconnect opening.

Abstract: A method includes forming a dummy pattern over test region of a substrate; forming an interlayer dielectric (ILD) layer laterally surrounding the dummy pattern; removing the dummy pattern to form an opening; forming a dielectric layer in the opening; performing a first testing process on the dielectric layer; performing an annealing process to the dielectric layer; and performing a second testing process on the annealed dielectric layer.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: Some embodiments relate to an integrated chip including a plurality of conductive structures over a substrate. A first dielectric layer is disposed laterally between the conductive structures. A spacer structure is disposed between the first dielectric layer and the plurality of conductive structures. An etch stop layer overlies the plurality of conductive structures. The etch stop layer is disposed on upper surfaces of the spacer structure and the first dielectric layer.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer arranged over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a barrier structure is arranged directly over the interconnect wire. The integrated chip further includes an etch stop layer arranged over the barrier structure and surrounds outer sidewalls of the barrier structure. A second interconnect dielectric layer is arranged over the etch stop layer, and an interconnect via extends through the second interconnect dielectric layer, the etch stop layer, and the barrier structure to contact the interconnect wire.

Abstract: A lighting device includes a housing, a light emitting module, a press plate and a fixing member. The housing has a bottom plate, a base and multiple stopping portions. The base protrudes from the bottom plate, and has a top surface and an inclined surface. The stopping portions are arranged at the bottom plate and extend to a bottom portion of the inclined surface of the base. The light emitting module includes a light panel and multiple light emitting elements arranged thereon. The light panel leans on the inclined surface and stopped by the stopping portions. The press plate is located at the top surface, and presses against the light panel. The fixing member fixes the press plate at the top surface to cause the press plate to press the light panel downward, so as to fix the light panel on the inclined surface.

Abstract: A liquid storage tank includes a housing, a piston located in the housing, a cover, an elastic element, and an outlet pipe. The cover is attached to the housing and has a support post extending toward the piston. The piston, the housing, and the cover define a tank chamber. The tank chamber is filled with cooling liquid. The elastic element is connected with the tank hosing and the piston. The elastic element is free from contact with the cooling liquid. The outlet pipe communicates with the tank chamber. An extension direction of an opening of the outlet pipe is not parallel to a direction of movement of the elastic element. When the cooling liquid is decreased, the piston compressed the tank chamber such that the elastic element is released. The tank chamber is continuously compressed by pairing the elastic element and the piston.

Abstract: A liquid storage tank includes a housing, a piston, a lower cover, an elastic element, and an outlet pipe. The piston is located in the housing. The lower cover is attached to the housing and has a support post extending toward the piston. The piston, the housing, and the lower cover define a tank chamber. The elastic element is connected with the tank hosing and the piston. The outlet pipe communicates with the tank chamber.

Abstract: A heat dissipation device and a manufacturing method thereof. The heat dissipation device includes a first chamber defining a first cavity, a second chamber defining a second cavity, and multiple connection members each defining a passageway. First and second ends of the connection members are respectively connected with the first and second chambers in communication with the first and second cavities through the passageways. A working fluid is contained in the first cavity. When the working fluid is heated, the working fluid is evaporated into vapor. The vapor passes through the passageways into the second cavity. After reaching the second cavity, the vapor is condensed into liquid state. Then, the liquid goes back into the first cavity through the passageways to complete a working cycle and achieve heat dissipation effect.

Abstract: A heat exchange apparatus includes an enclosure and a heat exchanger. The enclosure internally defines a first space and a second space isolated from each other, and is provided with a first and a second air inlet communicating with the first and the second space, respectively. The heat exchanger is arranged inside the enclosure and located between the first and the second space. By providing the heat exchanger between the first and the second space inside the enclosure, heat can be exchanged between the first and the second space to enable effectively upgraded heat exchange efficiency, and a device using the heat exchange apparatus is protected against invasion by foreign matters via the heat exchange apparatus.

Abstract: A heat dissipation device and a manufacturing method thereof. The heat dissipation device includes a first chamber defining a first cavity, a second chamber defining a second cavity, and multiple connection members each defining a passageway. First and second ends of the connection members are respectively connected with the first and second chambers in communication with the first and second cavities through the passageways. A working fluid is contained in the first cavity. When the working fluid is heated, the working fluid is evaporated into vapor. The vapor passes through the passageways into the second cavity. After reaching the second cavity, the vapor is condensed into liquid state. Then, the liquid goes back into the first cavity through the passageways to complete a working cycle and achieve heat dissipation effect.