Patents by Inventor Chih-Chien Pan

Chih-Chien Pan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11987431
    Abstract: A top-opening substrate carrier comprises a container body, a door member and at least one latching mechanism. The latching mechanism includes a rotary drive member, a first driven cam, a second driven cam, a first connecting rod, a second connecting rod, two longitudinal latching arms and two lateral latching arms. The first driven cam and the second driven cam are disposed at two sides of the rotary drive member. When the rotary drive member is rotated by force, it links and activates the first connecting rod and the second connecting rod to synchronously drive the first driven cam and the second driven cam to rotate, thereby driving the two longitudinal latching arms and the two lateral latching arms to project towards locking holes of the container body and locked, or retract from the locking holes of the container body and unlocked.
    Type: Grant
    Filed: March 27, 2023
    Date of Patent: May 21, 2024
    Assignee: GUDENG PRECISION INDUSTRIAL CO., LTD.
    Inventors: Ming-Chien Chiu, Yung-Chin Pan, Cheng-En Chung, Chih-Ming Lin, Po-Ting Lee, Wei-Chien Liu, Tzu-Ning Huang
  • Patent number: 11942403
    Abstract: In an embodiment, a package includes: an interposer having a first side; a first integrated circuit device attached to the first side of the interposer; a second integrated circuit device attached to the first side of the interposer; an underfill disposed beneath the first integrated circuit device and the second integrated circuit device; and an encapsulant disposed around the first integrated circuit device and the second integrated circuit device, a first portion of the encapsulant extending through the underfill, the first portion of the encapsulant physically disposed between the first integrated circuit device and the second integrated circuit device, the first portion of the encapsulant being planar with edges of the underfill and edges of the first and second integrated circuit devices.
    Type: Grant
    Filed: November 4, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chien Pan, Li-Hui Cheng, Chin-Fu Kao, Szu-Wei Lu
  • Publication number: 20240079399
    Abstract: A package structure and methods of forming a package structure are provided. The package structure includes a first die, a second die, a wall structure and an encapsulant. The second die is electrically bonded to the first die. The wall structure is located aside the second die and on the first die. The wall structure is in contact with the first die and a hole is defined within the wall structure for accommodating an optical element. The encapsulant laterally encapsulates the second die and the wall structure.
    Type: Application
    Filed: November 13, 2023
    Publication date: March 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chien Pan, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu
  • Publication number: 20240071857
    Abstract: A semiconductor device includes a package substrate, a package component and at least one adhesive pattern. The package component has a thermal interface material (TIM) layer thereon. The adhesive pattern has a first surface facing the package substrate and a second surface opposite to the first surface, and the second surface of the at least one adhesive pattern is substantially coplanar with a surface of the TIM layer.
    Type: Application
    Filed: August 31, 2022
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chien Pan, Pu Wang, Li-Hui Cheng, Ying-Ching Shih
  • Patent number: 11901255
    Abstract: A method of forming a semiconductor device includes attaching a first semiconductor device to a first surface of a substrate; forming a sacrificial structure on the first surface of the substrate around the first semiconductor device, the sacrificial structure encircling a first region of the first surface of the substrate; and forming an underfill material in the first region.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chien Pan, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu
  • Patent number: 11894287
    Abstract: Provided are a package structure and a method of forming the same. The package structure includes a first die, a second die group, an interposer, an underfill layer, a thermal interface material (TIM), and an adhesive pattern. The first die and the second die group are disposed side by side on the interposer. The underfill layer is disposed between the first die and the second die group. The adhesive pattern at least overlay the underfill layer between the first die and the second die group. The TIM has a bottom surface being in direct contact with the first die, the second die group, and the adhesive pattern. The adhesive pattern separates the underfill layer from the TIM.
    Type: Grant
    Filed: March 10, 2023
    Date of Patent: February 6, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu, Chih-Chien Pan
  • Patent number: 11855054
    Abstract: A package structure and methods of forming a package structure are provided. The package structure includes a first die, a second die, a wall structure and an encapsulant. The second die is electrically bonded to the first die. The wall structure is located aside the second die and on the first die. The wall structure is in contact with the first die and a hole is defined within the wall structure for accommodating an optical element. The encapsulant laterally encapsulates the second die and the wall structure.
    Type: Grant
    Filed: April 10, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chien Pan, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu
  • Publication number: 20230378130
    Abstract: A semiconductor structure includes a first semiconductor package, a second semiconductor package, a heat spreader and an dielectric layer. The first semiconductor package includes a plurality of first semiconductor chips and a first dielectric encapsulation layer disposed around the plurality of the first semiconductor chips. The second semiconductor package is disposed over and corresponds to one of the plurality of first semiconductor chips, wherein the second semiconductor package includes a plurality of second semiconductor chips and a second dielectric encapsulation layer disposed around the plurality of second semiconductor chips. The heat spreader is disposed over and corresponds to another of the plurality of first semiconductor chips. The dielectric layer is disposed over the first semiconductor package and around the second semiconductor package and the heat spreader.
    Type: Application
    Filed: July 12, 2023
    Publication date: November 23, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chien Pan, Pu Wang, Li-Hui Cheng, An-Jhih Su, Szu-Wei Lu
  • Publication number: 20230369283
    Abstract: A jig for manufacturing a semiconductor package includes a bottom piece and an upper piece. The bottom piece includes a base, a support plate, and at least one elastic connector. The support plate is located in a central region of the base. The at least one elastic connector is interposed between the support plate and the base. The upper piece includes a cap and outer flanges. The cap overlays the support plate when the upper piece is disposed on the bottom piece. The outer flanges are disposed at edges of the cap, connected with the cap. The outer flanges contact the base of the bottom piece when the upper piece is disposed on the bottom piece. The cap includes an opening which is a through hole. When the upper piece is disposed on the bottom piece, a vertical projection of the opening falls entirely on the support plate.
    Type: Application
    Filed: July 26, 2023
    Publication date: November 16, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Chih-Chien Pan, Pu Wang, Li-Hui Cheng, Szu-Wei Lu
  • Patent number: 11804468
    Abstract: A jig for manufacturing a semiconductor package includes a bottom piece and an upper piece. The bottom piece includes a base, a support plate, and at least one elastic connector. The support plate is located in a central region of the base. The at least one elastic connector is interposed between the support plate and the base. The upper piece includes a cap and outer flanges. The cap overlays the support plate when the upper piece is disposed on the bottom piece. The outer flanges are disposed at edges of the cap, connected with the cap. The outer flanges contact the base of the bottom piece when the upper piece is disposed on the bottom piece. The cap includes an opening which is a through hole. When the upper piece is disposed on the bottom piece, a vertical projection of the opening falls entirely on the support plate.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: October 31, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Chih-Chien Pan, Pu Wang, Li-Hui Cheng, Szu-Wei Lu
  • Publication number: 20230290714
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a first redistribution structure, a packaged device and a second redistribution structure. The packaged device is on a first side of the first redistribution structure and the second redistribution structure is on a second side of the first redistribution structure. An encapsulant is on the second side of the first redistribution structure and laterally around the second redistribution structure, wherein the encapsulant covers a periphery of the second redistribution structure such that an uncovered surface of the second redistribution structure is defined.
    Type: Application
    Filed: March 14, 2022
    Publication date: September 14, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ping-Yin Hsieh, Chih-Chien Pan, Li-Hui Cheng
  • Patent number: 11742323
    Abstract: A semiconductor structure includes a first semiconductor package, a second semiconductor package, a heat spreader and an underfill layer. The first semiconductor package includes a plurality of lower semiconductor chips and a first dielectric encapsulation layer disposed around the plurality of the lower semiconductor chips. The second semiconductor package is disposed over and corresponds to one of the plurality of lower semiconductor chips, wherein the second semiconductor package includes a plurality of upper semiconductor chips and a second dielectric encapsulation layer disposed around the plurality of upper semiconductor chips. The heat spreader is disposed over and corresponds to another of the plurality of lower semiconductor chips. The underfill layer is disposed over the first semiconductor package and around the second semiconductor package and the heat spreader.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: August 29, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chien Pan, Pu Wang, Li-Hui Cheng, An-Jhih Su, Szu-Wei Lu
  • Publication number: 20230253276
    Abstract: A method for forming a package structure is provided. The method includes bonding a package component to a substrate through a plurality of first connectors. The package component comprises a first semiconductor die and a second semiconductor die. The method also includes forming a dam structure over the substrate and surrounding the first connectors. A top surface of the dam structure is lower than a bottom surface of the package component. The method further includes filling an underfill layer in a space between the dam structure and the first connectors. In addition, the method includes removing the dam structure after the underfill layer is formed.
    Type: Application
    Filed: April 18, 2023
    Publication date: August 10, 2023
    Inventors: Chih-Hao CHEN, Chih-Chien PAN, Li-Hui CHENG, Chin-Fu KAO, Szu-Wei LU
  • Publication number: 20230230898
    Abstract: Provided are a package structure and a method of forming the same. The package structure includes a first die, a second die group, an interposer, an underfill layer, a thermal interface material (TIM), and an adhesive pattern. The first die and the second die group are disposed side by side on the interposer. The underfill layer is disposed between the first die and the second die group. The adhesive pattern at least overlay the underfill layer between the first die and the second die group. The TIM has a bottom surface being in direct contact with the first die, the second die group, and the adhesive pattern. The adhesive pattern separates the underfill layer from the TIM.
    Type: Application
    Filed: March 10, 2023
    Publication date: July 20, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu, Chih-Chien Pan
  • Patent number: 11664286
    Abstract: A method for forming a package structure is provided. The method for forming a package structure includes bonding a package component to a first surface of a substrate through a plurality of first connectors. The package component includes a first semiconductor die and a second semiconductor die. The method also includes forming a dam structure over the first surface of the substrate. The dam structure is around and separated from the package component, and a top surface of the dam structure is higher than a top surface of the package component. The method further includes forming an underfill layer between the dam structure and the package component. In addition, the method includes removing the dam structure after the underfill layer is formed.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: May 30, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Hao Chen, Chih-Chien Pan, Li-Hui Cheng, Chin-Fu Kao, Szu-Wei Lu
  • Patent number: 11626344
    Abstract: Provided are a package structure and a method of forming the same. The package structure includes a first die, a second die group, an interposer, an underfill layer, a thermal interface material (TIM), and an adhesive pattern. The first die and the second die group are disposed side by side on the interposer. The underfill layer is disposed between the first die and the second die group. The adhesive pattern at least overlay the underfill layer between the first die and the second die group. The TIM has a bottom surface being in direct contact with the first die, the second die group, and the adhesive pattern. The adhesive pattern separates the underfill layer from the TIM.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: April 11, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu, Chih-Chien Pan
  • Publication number: 20230052821
    Abstract: In an embodiment, a package includes: an interposer having a first side; a first integrated circuit device attached to the first side of the interposer; a second integrated circuit device attached to the first side of the interposer; an underfill disposed beneath the first integrated circuit device and the second integrated circuit device; and an encapsulant disposed around the first integrated circuit device and the second integrated circuit device, a first portion of the encapsulant extending through the underfill, the first portion of the encapsulant physically disposed between the first integrated circuit device and the second integrated circuit device, the first portion of the encapsulant being planar with edges of the underfill and edges of the first and second integrated circuit devices.
    Type: Application
    Filed: November 4, 2022
    Publication date: February 16, 2023
    Inventors: Chih-Chien Pan, Li-Hui Cheng, Chin-Fu Kao, Szu-Wei Lu
  • Publication number: 20220359476
    Abstract: A package structure includes a circuit substrate, a semiconductor package, a lid structure, a passive device and a barrier structure. The semiconductor package is disposed on and electrically connected to the circuit substrate. The lid structure is disposed on the circuit substrate covering the semiconductor package. The lid structure is attached to the circuit substrate through an adhesive material. The passive device is disposed on the circuit substrate in between the semiconductor package and the lid structure. The barrier structure is separating the passive device from the lid structure and the adhesive material, and the barrier structure is in contact with the adhesive material.
    Type: Application
    Filed: July 22, 2022
    Publication date: November 10, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Pin Hu, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu, Wen-Hsin Wei, Chih-Chien Pan
  • Publication number: 20220359331
    Abstract: A method of forming a semiconductor device includes attaching a first semiconductor device to a first surface of a substrate; forming a sacrificial structure on the first surface of the substrate around the first semiconductor device, the sacrificial structure encircling a first region of the first surface of the substrate; and forming an underfill material in the first region.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 10, 2022
    Inventors: Chih-Chien Pan, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu
  • Patent number: 11495526
    Abstract: In an embodiment, a package includes: an interposer having a first side; a first integrated circuit device attached to the first side of the interposer; a second integrated circuit device attached to the first side of the interposer; an underfill disposed beneath the first integrated circuit device and the second integrated circuit device; and an encapsulant disposed around the first integrated circuit device and the second integrated circuit device, a first portion of the encapsulant extending through the underfill, the first portion of the encapsulant physically disposed between the first integrated circuit device and the second integrated circuit device, the first portion of the encapsulant being planar with edges of the underfill and edges of the first and second integrated circuit devices.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: November 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chien Pan, Li-Hui Cheng, Chin-Fu Kao, Szu-Wei Lu